SAR ADC Comparator Metastability Handling for Bit Accuracy
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Solution Overview
Problem
Successive approximation type Analog to Digital Converters (ADCs) face large conversion errors due to prolonged metastable states in comparators, which can lead to incorrect digital code generation, especially when the difference between input and reference voltages is small.
Innovation Solution
Incorporating a metastable state detection circuit that monitors the comparator's output and forcibly determines the bit value of the next lower-order bit when a metastable state is detected, ensuring accurate conversion by adjusting the reference voltage generation and bit determination timing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the comparator is used to compare input voltage and reference voltage in a successive approximation ADC, then the conversion process can be implemented, but the prolonged metastable state causes large conversion errors
Solution Approach 1:
The patent applies preliminary action by detecting the metastable state of the comparator before the regeneration time expires. The detection unit monitors the comparator output and identifies when it enters a metastable state, allowing the system to take preliminary corrective action (forcing a determination) before the prolonged metastable state can cause conversion errors.
Solution Approach 2:
The patent converts the harmful metastable state into a beneficial detection opportunity. By monitoring the comparator output for metastable conditions, the system can identify when intervention is needed and force a determination, thereby converting the potentially harmful prolonged metastable state into a controlled condition that prevents conversion errors.
2Reliability
If the comparator operates without metastable state detection, then the device complexity is lower, but conversion errors increase due to prolonged metastable states
Solution Approach 1:
The patent introduces an intermediary detection unit that monitors the comparator output without disrupting the normal comparison operation. This intermediary component detects metastable states and triggers the forcing determination unit, thereby improving conversion accuracy while adding only minimal circuit complexity through a dedicated monitoring mechanism.
Solution Approach 2:
The system performs self-service by having the detection unit automatically monitor the comparator state and trigger appropriate responses. The metastable state detection and forcing determination operate autonomously based on the comparator's own output conditions, eliminating the need for external intervention or complex control logic.
3Measurement precision
If the bit determination is delayed to allow comparator stabilization, then conversion accuracy improves, but the conversion time increases
Solution Approach 1:
The patent applies preliminary action by detecting metastable states early in the comparison process. When a metastable state is detected, the system immediately forces a determination rather than waiting for natural stabilization, thereby maintaining bit determination accuracy while significantly reducing the time required for conversion.
Solution Approach 2:
The patent introduces dynamic adaptation by adjusting the determination timing based on the actual comparator state. Instead of using a fixed delay, the system dynamically responds to detected metastable conditions, forcing determination only when necessary, thereby optimizing both accuracy and speed according to real-time operational conditions.
Data Source
AI summary
According to the present invention, a successive approximation type analog-digital converter includes: a comparator outputting a result of comparing an analog signal and a reference voltage; a register storing a digital value corresponding to the result of comparison and outputting a digital signal; a detection unit detecting whether the comparator is in a stable state or not for each bit; and a bit determination unit storing, if the comparator is not stable, as a bit value of a bit which is one bit lower-order than a corresponding detection bit, a value obtained by inverting a final determined bit value of the detection bit in the register instead of the comparison result of the comparator.