ADC Correction Circuit for Settling Error in MSB Conversion

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Solution Overview

Problem

Conventional analog-to-digital converters (ADCs) face settling errors during initial stages of conversion due to insufficient settling time, leading to incorrect determination of the most significant bit (MSB) of the digital output signal.

Innovation Solution

Incorporating a correction control circuit that adjusts the least significant bit (LSB) of the digital output signal based on comparison results, and using different clock frequencies or dual DAC types for upper and lower bit determination to mitigate settling errors.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If the DAC generates conversion voltage with large swing width at initial stage, then the conversion range covers the full input voltage range, but the settling time becomes insufficient causing settling errors

Engineering Contradiction:
Improveconversion voltage swing rangeVSAvoidconversion accuracy
Core Design Contradiction:
Adaptability or versatilityVSMeasurement precision

Solution Approach 1:

The conversion process is divided into two stages: initial conversion phase and correction phase. The DAC operation is segmented into normal mode (for bits 3-1) and correction mode (for bit 0), allowing different swing widths at different times to resolve the contradiction between coverage and precision

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The MSB is determined first in the initial conversion phase, establishing a preliminary digital output that may contain errors. Then the correction phase adjusts the LSB based on comparing the initial conversion result with the actual input voltage, preliminarily identifying and correcting the settling error

Inventive Principle:
Principle #10Preliminary action

2Productivity

If the conversion process is completed quickly, then the conversion speed increases, but the settling time becomes insufficient leading to incorrect MSB determination

Engineering Contradiction:
Improveconversion speedVSAvoidconversion reliability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The conversion is segmented into rapid initial conversion (determining bits 3-1 quickly) followed by a correction phase (adjusting bit 0). This segmentation allows the system to prioritize speed for most bits while dedicating specific correction time to ensure reliability of the final result

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The comparator continuously compares the DAC output voltage with the input voltage during the correction phase. This feedback mechanism identifies whether the initial MSB determination was correct and guides the adjustment of the LSB to achieve the correct final digital output

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS12476647B2Analog-to-digital converter
Publication Date: 2025.11.18 SK HYNIX INC
  • US12476647B2 patent drawing
  • US12476647B2 patent drawing
  • US12476647B2 patent drawing

AI summary

An analog-to-digital converter includes a comparator configured to compare an input voltage and a conversion voltage and to generate a comparison result; a digital-to-analog converter configured to generate the conversion voltage according to a digital output signal; and a control circuit including a conversion control circuit configured to determine the digital output signal corresponding to the input voltage based on the comparison result; and a correction control circuit configured to correct an error of the digital output signal by increasing or decreasing the digital output signal based on the comparison result after the digital output signal is determined.