High-Resolution ADC Architecture With Quantization Noise Subtraction
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Solution Overview
Problem
Prior art analog to digital converters (ADCs) are power consumptive, provide low resolution, and are not suitable for applications with limited power budgets or high performance requirements, failing to adequately serve various industrial and medical applications.
Innovation Solution
The development of novel ADC designs and architectures that enable high-resolution digital format data conversion with simultaneous drive and sense capabilities, utilizing a comparator and digital circuit to process analog signals into high-resolution digital outputs with low power consumption, suitable for a broad range of applications including industrial and medical uses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If prior art ADC designs are used, then device complexity is reduced, but measurement precision and resolution deteriorate
Solution Approach 1:
The ADC is divided into multiple parallel sub-ADCs (first and second ADCs) that process different portions of the input signal simultaneously. Each sub-ADC has simplified internal structure, but their parallel combination achieves high resolution through coordinated operation and digital processing of multiple lower-resolution outputs.
Solution Approach 2:
The patent implements a hierarchical structure where multiple levels of signal processing are nested within the ADC architecture. The input signal is split and processed through nested stages of comparison and digitization, with each stage building upon the previous to achieve cumulative resolution enhancement.
2Use of energy by moving object
If prior art ADC designs are used, then ease of manufacture is improved, but use of energy deteriorates
Solution Approach 1:
The ADC employs periodic switching and sampling mechanisms where capacitors are charged and discharged in controlled cycles, and switches are toggled at specific frequencies. This periodic operation allows the circuit to process signals efficiently over time while maintaining low average power consumption through duty-cycled operation.
Solution Approach 2:
The patent implements self-calibration and auto-zeroing circuits that automatically compensate for offset errors and drift without external intervention. The ADC uses its own internal resources to perform calibration sequences, eliminating the need for external calibration equipment and reducing overall system power requirements.
3Productivity
If prior art ADC designs are used, then device complexity is reduced, but productivity deteriorates
Solution Approach 1:
The input signal bandwidth is divided and processed in parallel by multiple sub-ADC channels, each handling a portion of the frequency spectrum or signal range. This parallel segmentation allows the system to achieve high overall bandwidth by summing the capabilities of individual simpler channels.
Solution Approach 2:
The patent transitions from single-channel sequential processing to multi-channel parallel processing, adding a spatial dimension to the signal processing architecture. By processing multiple signal streams simultaneously across different channels and then combining them digitally, the system achieves higher effective bandwidth without proportionally increasing per-channel complexity.
Data Source
AI summary
A high resolution analog to digital converter (ADC) with improved bandwidth senses an analog signal (e.g., a load current) to generate a digital signal. The ADC operates based on a load voltage produced based on charging of an element (e.g., a capacitor) by a load current and a digital to analog converter (DAC) output current (e.g., from a N-bit DAC). The ADC generates a digital output signal representative of a difference between the load voltage and a reference voltage. This digital output signal is used directly, or after digital signal processing, to operate an N-bit DAC to generate a DAC output current that tracks the load current. In addition, quantization noise is subtracted from the digital output signal thereby extending the operational bandwidth of the ADC. In certain examples, the operational bandwidth of the ADC extends up to 100s of kHz (e.g., 200-300 kHz), or even higher.