ADC Nonlinearity Compensation Using Interpolated Error Estimation
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Solution Overview
Problem
Analog-to-digital converters (ADCs) face challenges in compensating for nonlinear distortion, which increases signal bandwidth, necessitating higher sampling rates that are undesirable due to increased circuit component demands and high computational complexity of inverse Volterra models for high nonlinearity orders and long memory.
Innovation Solution
An estimation unit and compensation circuit that estimate and compensate for nonlinearity errors by interpolating and filtering digital input signals to generate error signals, allowing for accurate correction without increasing the sampling rate, using a discrete-time model with polyphase components and linear/nonlinear filter units to produce a better digital output signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the sampling rate of the ADC is increased to capture the nonlinearly distorted signal, then the nonlinear distortion can be properly compensated in the digital domain, but the speed requirements on circuit components of the ADC increase
Solution Approach 1:
The patent segments the nonlinear distortion compensation into multiple computational stages (Volterra kernel estimation, error signal generation, and error subtraction) that can be performed at the original sampling rate, avoiding the need to increase the ADC sampling rate while still achieving accurate compensation
Solution Approach 2:
The patent introduces an intermediary error signal that represents the nonlinear distortion components. This error signal is generated through digital signal processing at the original sampling rate and then subtracted from the ADC output, serving as a mediator that enables compensation without requiring higher sampling rates
2Measurement precision
If an inverse Volterra model is used to compensate for nonlinear distortion, then the nonlinear distortion can be corrected in the digital domain, but the computational complexity increases especially for high nonlinearity orders and long memory
Solution Approach 1:
The patent segments the Volterra model computation into distinct functional blocks (filter units for different kernel estimates, nonlinearity units for power operations, and error signal generation units) that can be independently optimized and implemented, reducing overall computational complexity while maintaining accuracy
Solution Approach 2:
The patent computes only the necessary Volterra kernel components required for effective distortion compensation rather than computing all possible kernel combinations, reducing computational complexity while maintaining sufficient compensation accuracy for practical applications
Data Source
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AI summary
An estimation unit (30, 30a-c) for estimating a nonlinearity error of a conversion circuit (10), such as an ADC, adapted to receive a continuous-time input signal and output a digital output signal. The continuous-time input signal is essentially bandlimited to an angular frequency band [?1, ?2 ], where ?1 > (L-1)p/T, ?2Lp/T, L is a positive integer, and T is a sample period of the conversion circuit. The estimation unit (30, 30a-c) comprises an input port (32, 32a-c) for receiving a digital input signal having a first sample rate 1/T and an output port (34, 34a-c) for outputting a digital estimated error signal also having the first sample rate. For each integer P_k in a set of integers, the estimation unit comprises a first linear filter unit (100-k) for generating a first signal s 1(n) as a linear function of the digital input signal, an interpolation unit (105-k) for interpolating the first signal s 1(n) to generate a second signal s 2(m) having a second sample rate which is a factor L·R_k higher than the first sample rate, wherein L·R_k = ?2·T·P_k/p, a nonlinearity unit (110-k) for generating a third signal s 3(m) as (s 2(m)) P _ k , and a second linear filter unit (115-k) for generating a component of the estimated error signal based on the third signal s 3(m), wherein said component has the first sample rate. Furthermore, the estimation unit comprises an adder circuit (117) for generating the estimated error signal as the sum of the components of the estimated error signal. Moreover, a compensation circuit (20) comprising the estimation unit, corresponding methods for estimating and compensating nonlinearity errors, a computer program product, a computer readable medium, and a hardware-description entity are also disclosed.