ADC Digital Calibration Loop for Comparator Offset Correction

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Solution Overview

Problem

The reduction in transistor gate size in submicron-scale CMOS comparators increases intrinsic offset voltage, affecting ADC accuracy by requiring comparison of analog signals to both reference and offset voltages, leading to decreased accuracy and signal-to-noise ratio.

Innovation Solution

A digital calibration loop is implemented in the ADC to counter the effects of offset voltage by determining and adjusting a calibration voltage, ensuring the ADC compares only the reference voltage, thereby maintaining accuracy and reducing power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If the transistor gate size is reduced to submicron scale, then power consumption is reduced, but offset voltage increases and ADC accuracy deteriorates

Engineering Contradiction:

Improvepower consumptionVSAvoidADC accuracy

Core Design Contradiction:

Use of energy by moving objectVSMeasurement precision

Solution Approach 1:

The patent applies preliminary action by performing offset voltage calibration before normal ADC operation. The calibration circuit pre-determines the offset voltage value and stores it in a lookup table, so that during normal operation, the pre-calculated correction values are applied without requiring real-time calibration, thus maintaining accuracy while enabling low-power submicron operation

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent implements feedback through a calibration loop that measures the actual offset voltage and uses this information to generate correction values. The system continuously monitors and adjusts for offset voltage effects by comparing ADC outputs and applying compensating corrections based on the measured offset characteristics

Inventive Principle:

Principle #23Feedback

2Volume of moving object

If the transistor gate size is reduced to submicron scale, then comparator size is reduced, but offset voltage increases and signal-to-noise ratio deteriorates

Engineering Contradiction:

Improvecomparator sizeVSAvoidsignal-to-noise ratio

Core Design Contradiction:

Volume of moving objectVSObject-affected harmful factors

Solution Approach 1:

The patent extracts the offset voltage as a separate measurable parameter from the overall ADC operation. By isolating and measuring the offset voltage component independently through calibration procedures, the system can remove its harmful effects through digital correction, thereby separating the size reduction benefit from the offset voltage penalty

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent converts the harmful offset voltage effect into a useful calibration signal. The offset voltage, initially a harmful artifact of small comparator size, becomes the basis for generating correction values that improve accuracy. The calibration process transforms the offset voltage from a problem into a diagnostic tool for system characterization

Inventive Principle:

Principle #22Blessing in disguise (Convert harm into benefit)

Data Source

PatentUS7623050B2Digital calibration loop for an analog to digital converter

Publication Date: 2009.11.24 AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE LTD

AI summary

A method and apparatus to counter effects of an offset voltage by calibrating an analog-to-digital converter (ADC). A digital calibration loop minimizes the effects of offset voltage to improve ADC accuracy as well as provide a low-power, submicron-scale ADC. A calibration circuit senses an ADC output and adjusts a variable calibration voltage to counter the effects of the offset voltage. Reduction of the offset voltage effects increases the ADC accuracy.