Multi-Stage ADC Offset Cancellation With Concurrent Settling
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Solution Overview
Problem
Existing multi-stage analog-to-digital converter (ADC) circuits require additional time for offset cancellation, which increases the overall on-time and power consumption.
Innovation Solution
The proposed solution combines the settling time of a signal conditioning circuit and the residue amplifier to cancel the offset of the signal conditioning circuit, allowing them to settle concurrently rather than sequentially.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If offset cancellation is performed sequentially before conversion, then offset accuracy is improved, but conversion time increases
Solution Approach 1:
The patent combines the offset cancellation operation with the conversion operation by performing both simultaneously in the same circuit stage. The residue amplifier that normally only amplifies the residue signal is configured to also perform the offset cancellation by subtracting the stored offset value from the sum of the sampled signal and offset, thereby eliminating the need for a separate sequential offset cancellation step and reducing total conversion time while maintaining accuracy
Solution Approach 2:
The patent enables continuous operation by allowing the residue amplifier to perform dual functions - amplifying the residue signal and canceling the offset - in a continuous manner without interrupting the conversion process. This eliminates idle time between offset cancellation and conversion, maintaining continuous useful action throughout the circuit operation
2Device complexity
If offset cancellation is performed sequentially, then circuit simplicity is maintained, but power consumption increases
Solution Approach 1:
The patent merges the offset cancellation function into the existing residue amplifier circuit, which already contains the necessary subtraction and amplification functionality. By configuring the residue amplifier to perform both offset cancellation and residue amplification in one operation, the patent avoids adding separate dedicated offset cancellation circuitry, thereby maintaining circuit simplicity while reducing power consumption through consolidated operation
3Measurement precision
If the signal conditioning circuit and residue amplifier settle sequentially, then settling accuracy is improved, but overall on-time increases
Solution Approach 1:
The patent merges the settling processes of the signal conditioning circuit and residue amplifier by configuring them to settle simultaneously during the same time interval. The control circuit coordinates the timing so that both circuits complete their settling within the same conversion cycle, allowing their settling times to overlap rather than add up, thereby reducing total on-time while maintaining the settling accuracy of both circuits
Solution Approach 2:
The patent performs preliminary sampling of the offset value and stores it in the sample-and-hold circuit before the conversion process begins. This preliminary action prepares the offset value in advance, allowing the residue amplifier to immediately use it for concurrent offset cancellation and settling without waiting for sequential preparation, thereby reducing the overall on-time required
Data Source
Figure 1A~1B
Figure 1C~1D
Figure 2
AI summary
Techniques to reduce the on-time of a multi-stage ADC circuit by combining the settling time of a signal conditioning circuit, e.g., buffer circuit, and the setting time of a residue amplifier when cancelling the offset of the signal conditioning circuit. The techniques can allow the signal conditioning circuit and the residue amplifier to settle together.