ADC Offset Calibration Using Differential Delta Voltages
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Solution Overview
Problem
Analog to digital converters (ADCs) suffer from offset error voltage, causing their digital output to deviate from the expected value, necessitating a calibration mechanism to correct this error for proper functioning.
Innovation Solution
A method involving a digital to analog converter generating positive and negative delta voltages, a comparator to generate digital output values, a logic circuit to determine a digital quantization code from the sum of these values, and a calibration circuit to eliminate the offset error using this code.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If an ADC is used to convert analog input voltage to digital output value, then digital conversion is achieved, but offset error voltage causes the digital output to deviate from the expected value
Solution Approach 1:
The patent applies preliminary action by performing calibration before normal ADC operation. The calibration process generates positive and negative delta voltages, obtains corresponding digital output values, calculates an offset error value, and stores it for subsequent correction. This preliminary calibration ensures that the ADC output accuracy is improved before actual conversion tasks begin.
Solution Approach 2:
The patent converts the harmful offset error voltage into a beneficial calibration parameter. By intentionally generating controlled positive and negative delta voltages and measuring their digital output values, the system identifies the offset error and uses it to correct future conversions. The harmful offset error is transformed into useful calibration information that improves measurement precision.
2Measurement precision
If a calibration mechanism is introduced to correct offset error, then digital output accuracy is improved, but device complexity increases
Solution Approach 1:
The patent merges the calibration function with the existing ADC structure by integrating the calibration circuit with the comparator and digital output generation logic. The calibration process uses the same comparator and digital output paths as normal operation, combining multiple functions into existing components rather than adding entirely separate calibration hardware.
Solution Approach 2:
The ADC system performs self-calibration by using its own internal components (DAC, comparator, logic circuit) to generate calibration signals and measure offset errors. The calibration process is autonomous, requiring no external calibration equipment, and the system uses its own digital output values to calculate and store the offset error correction parameter.
Data Source
AI summary
According to an aspect of the disclosure, the disclosure provides an ADC which includes not limited to: a DAC configured to generate a positive input delta voltage and a negative input delta voltage, a comparator electrically connected to the DAC and configured to receive the positive input delta voltage to generate a first digital output value and to receive the negative input delta voltage to generate a second digital output value, a logic circuit configured to receive, from the comparator, the first digital output value and the second digital output value to generate a digital quantization code according to half of a sum of the first digital output value and the second digital output value, and a calibration circuit configured to receive the digital quantization code from the logic circuit and calibrate an output of the ADC according to the digital quantization code to eliminate an offset error value.