Flash ADC Comparator Offset Correction with Shared Digital Assist
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Solution Overview
Problem
In analog-to-digital conversion circuits, the generation of offset voltage due to transistor characteristic variations and asymmetric circuit layouts leads to incorrect comparison results, and existing solutions like OFC circuits increase the number of signal lines required, causing circuit crowding as the number of bits increases.
Innovation Solution
An analog-to-digital conversion apparatus with a switching unit, conversion unit, and correction data generation unit that compares reference voltages and input signals in parallel, generates correction data to adjust the input signal voltage, and outputs this data to correct offset voltages in comparators, reducing the need for additional signal lines by using a digital assist circuit to control the switching and correction process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If an OFC circuit is provided for every comparator in a parallel comparison system, then offset voltage correction is achieved, but the number of signal lines increases exponentially with the number of bits
Solution Approach 1:
The patent merges the offset correction function into a single shared OFC circuit that serves all comparators. Instead of having separate OFC circuits for each comparator, one OFC circuit is shared across all comparators, and it sequentially corrects offset voltages for each comparator by switching between them using switching elements. This reduces the number of signal lines from exponential to linear scale.
Solution Approach 2:
The patent introduces dynamic switching to enable a single OFC circuit to serve multiple comparators. Switching elements dynamically connect the shared OFC circuit to different comparators in sequence, allowing the system to adapt the correction function to each comparator without requiring dedicated static connections. This dynamic approach reduces the overall circuit complexity while maintaining correction capability.
2Measurement precision
If the number of bits of digital signal is increased, then conversion precision is improved, but the circuit becomes more crowded due to increased signal lines
Solution Approach 1:
The patent merges multiple offset correction functions into a single shared OFC circuit that sequentially serves all comparators. This consolidation dramatically reduces the number of signal lines required, allowing the circuit to scale to higher bit resolutions without proportional increases in circuit area. The shared circuit approach enables high-precision conversion while maintaining compact layout.
Solution Approach 2:
The patent introduces a time dimension to the offset correction process by sequentially correcting different comparators rather than simultaneously. This temporal multiplexing allows a single OFC circuit to handle multiple comparators, effectively trading time for space and reducing the circuit area required for high-bit precision conversion.
3Measurement precision
If separate OFC circuits are connected to each comparator, then offset correction is effective, but the circuit layout becomes asymmetric and increases manufacturing difficulty
Solution Approach 1:
The patent merges multiple separate OFC circuits into a single shared OFC circuit that serves all comparators. This consolidation creates a more symmetric and regular circuit layout, as the single OFC circuit can be placed in a centralized location with systematic connections to all comparators. The regular switching pattern simplifies manufacturing processes and improves layout symmetry compared to having scattered separate OFC circuits.
Data Source
AI summary
An analog-to-digital conversion apparatus has a plurality of comparators configured to compare each of a plurality of different reference voltages and an input signal voltage in a parallel manner, a switch unit configured to switch the input signal voltage to a voltage corresponding to an analog input signal voltage or one of the plurality of reference voltages, an encoder configured to convert comparison results of the plurality of comparators into digital signals, and a digital assist circuit configured to control the switch unit so that the input signal voltage has a potential corresponding to the reference voltage in the comparator being the correction target among the plurality of comparators, to generate correction data for correcting the offset voltage generated in the comparator being the correction target based on the digital signal and to output it to the comparator being the correction target.