ADC Signal Calibration Using Offset Tables and Parallel Channels

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Solution Overview

Problem

Analog-to-digital conversion apparatuses suffer from capacitance offsets that result in errors, necessitating a calibration technology to achieve optimal signal conversion.

Innovation Solution

The apparatus employs a signal calibration mechanism with a conversion circuit, calibration circuit, and digital filtering circuit, utilizing time-division switching of capacitors and capacitance offset tables to generate and update digital signals, followed by inverse filtering to correct capacitance offsets.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If capacitance offset calibration is performed using traditional methods, then conversion accuracy is improved, but conversion time increases due to sequential calibration steps

Engineering Contradiction:
Improveconversion accuracyVSAvoidconversion time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The calibration process is segmented into multiple parallel channels (odd and even conversion circuits), each with dedicated calibration circuits operating simultaneously. This segmentation allows calibration to occur in parallel rather than sequentially, reducing total calibration time while maintaining accuracy for each channel.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Capacitance offset tables are pre-calculated and stored before actual signal conversion. During conversion, the calibration circuits directly reference these pre-computed tables to apply corrections, eliminating the need for real-time calibration calculations and reducing conversion time.

Inventive Principle:
Principle #10Preliminary action

2Productivity

If multiple calibration circuits operate in parallel, then calibration speed is improved, but device complexity increases

Engineering Contradiction:
Improvecalibration speedVSAvoiddevice complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

Multiple calibration circuits are designed with identical structures and functions, each handling a specific conversion channel. This universal design allows parallel operation for improved speed while using standardized components that simplify overall system design and maintenance despite the increased number of circuits.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The calibration circuit design is copied across multiple channels (odd and even), with each copy handling a specific set of capacitors. This replication enables parallel calibration operations while using proven, tested circuit designs, reducing the complexity of designing entirely new calibration mechanisms for each channel.

Inventive Principle:
Principle #26Copying

3Measurement precision

If capacitance offset tables are updated continuously, then conversion accuracy is improved, but computational load increases

Engineering Contradiction:
Improveconversion accuracyVSAvoidcomputational load
Core Design Contradiction:
Measurement precisionVSUse of energy by moving object

Solution Approach 1:

Capacitance offset tables are pre-calculated and stored in memory before actual signal conversion operations. During conversion, the calibration circuits simply retrieve and apply the pre-computed correction values from these tables, avoiding the need for continuous real-time calculations and reducing computational load while maintaining accuracy.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS20260025145A1Analog-to-digital conversion apparatus and method having signal calibration mechanism
Publication Date: 2026.01.22 REALTEK SEMICON CORP
  • US20260025145A1 patent drawing
  • US20260025145A1 patent drawing
  • US20260025145A1 patent drawing

AI summary

An analog-to-digital conversion apparatus having signal calibration mechanism is provided. Capacitors in an odd and an even conversion circuits in a conversion circuit are switched to perform conversion on a signal feeding to generate odd and even digital signals such that an odd and an even calibration circuit performs mapping thereon according to odd and even capacitance offset tables to generate odd and even calibrated signals. A digital filtering circuit performs digital filtering on the odd and the even calibrated signals according to odd and even filtering parameters and merges the filtered results to generate a merged output digital signal such that a calibration parameter calculation circuit performs filtering thereon to generate an odd and an even inverted error signal and further performs calculation thereon with the corresponding odd and even digital signals to generate odd and even updating parameter to update the odd and the even capacitance offset tables.