Lookahead Pipelined ADC Using Open-Loop Residue Amplifiers
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Solution Overview
Problem
High-speed analog-to-digital converters (ADCs) face challenges in achieving both high speed and high accuracy while maintaining low power consumption, particularly for 10 Gbit/s serial data transmission applications, as existing technologies consume excessive power and have limitations in offset requirements and comparator metastability.
Innovation Solution
A lookahead pipelined ADC architecture using open-loop residue amplifiers with digital calibration, which increases sampling rate and reduces power consumption by removing the need for linear amplifiers and compensating for non-linearity, and employing a sub-radix architecture with redundancy to enhance accuracy and manufacturability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If closed-loop operational amplifiers are used in pipeline ADC stages, then linearity and accuracy are improved, but power consumption increases significantly
Solution Approach 1:
The patent extracts the feedback loop from the operational amplifier configuration, transitioning from closed-loop to open-loop architecture. This removes the power-consuming feedback mechanism while retaining the essential amplification function through carefully designed gain stages and calibration circuits.
Solution Approach 2:
The patent changes the operating parameters by using open-loop amplifiers with controlled gain values (e.g., G=2) instead of high-gain closed-loop amplifiers. Combined with digital calibration that compensates for gain and offset errors, this parameter change achieves comparable accuracy at lower power consumption.
2Productivity
If higher conversion rates are achieved in ADCs, then data transmission speed is improved, but power consumption increases
Solution Approach 1:
The patent segments the ADC into multiple pipeline stages, each operating at a lower individual rate but collectively achieving high throughput. This segmentation allows parallel processing of different signal components, improving overall conversion rate without proportionally increasing power consumption in each stage.
Solution Approach 2:
The patent employs periodic calibration sequences where calibration operations are interleaved with normal conversion operations. This periodic action allows the system to maintain high average conversion rates while periodically correcting errors, effectively managing power consumption through time-multiplexed operation.
3Use of energy by moving object
If open-loop amplifiers are used to reduce power consumption, then non-linearity increases, but accuracy deteriorates
Solution Approach 1:
The patent introduces digital feedback mechanisms where the output of each stage is fed back through digital-to-analog converters and subtracted from the input signal. This digital feedback loop compensates for the non-linearity of open-loop amplifiers, maintaining accuracy while enjoying the power benefits of open-loop operation.
Solution Approach 2:
The patent substitutes analog compensation mechanisms with digital calibration and correction circuits. Instead of using complex analog linearization circuits that would consume power, the system uses digital processing to correct non-linearity errors, achieving accuracy improvement with minimal additional power consumption.
Data Source
AI summary
A lookahead pipelined ADC architecture uses open-loop residue amplifiers with calibration. This approach is able to achieve a high-speed, high-accuracy ADC with reduced power consumption. In one aspect, an ADC pipeline unit includes a plurality of lookahead pipeline stages (i.e., an ADC lookahead pipeline) coupled to a calibration unit. The ADC lookahead pipeline uses open-loop residue amplifiers. The calibration unit compensates for non-linearity in the open-loop amplifiers.