Pipeline ADC Inter-Stage Gain Calibration with Sub-ADC Perturbation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Pipeline ADCs face significant errors due to deviations from nominal inter-stage gain factors, which are not efficiently corrected in existing technologies.
Innovation Solution
A self-calibrating pipeline ADC system that includes a first conversion stage with a sub-ADC, sub-DAC, analog summing circuit, amplifier, and adaptation circuit to adjust the weighting factor based on the correlation between the control code and digital codes, ensuring the inter-stage gain error is corrected.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a pipeline ADC uses inter-stage gain amplification to efficiently utilize the dynamic range of succeeding stages, then the conversion efficiency and dynamic range utilization are improved, but the error due to deviation from nominal inter-stage gain factor increases
Solution Approach 1:
The patent introduces a feedback mechanism where the digital output code from the succeeding stage is fed back to the current stage. This feedback loop allows the system to detect and correct errors caused by inter-stage gain deviations. The digital summing circuit combines the intermediate digital code with the fed-back digital code, effectively compensating for gain errors and resolving the contradiction between conversion efficiency and accuracy.
Solution Approach 2:
The patent dynamically adjusts the weighting factor in the digital summing circuit based on the actual inter-stage gain factor. By changing the parameter (weighting factor) to match the actual gain deviation, the system compensates for errors while maintaining the benefits of inter-stage gain amplification. This allows the system to adapt to gain variations and maintain high conversion accuracy.
2Adaptability or versatility
If the inter-stage gain factor deviates from the nominal value, then the actual conversion performance may vary, but the error due to gain mismatch increases significantly
Solution Approach 1:
The patent implements a self-calibrating mechanism where the ADC system automatically detects and corrects its own gain errors without external intervention. The digital feedback loop enables the system to self-adjust by combining the intermediate code with the fed-back code, effectively compensating for gain deviations and maintaining high conversion accuracy despite variations in inter-stage gain factor.
3Measurement precision
If the digital input code is scaled to account for inter-stage gain, then the conversion accuracy improves, but the complexity of the digital processing increases
Solution Approach 1:
The patent merges the gain compensation function with the existing digital summing operation. Instead of adding a separate scaling operation, the system combines the intermediate digital code and the fed-back digital code in a single summing circuit. This integration approach maintains conversion accuracy while minimizing additional digital processing complexity.
Data Source
AI summary
An inter-stage gain of a conversion stage of a pipeline ADC is calibrated by imposing a perturbation to a sub-ADC within the conversion stage and adjusting a gain factor in a closed loop manner so as to make a conversion output substantially independent of the perturbation.