ADC Input Sampling Pre-Charge Circuit for Fast Accurate Settling
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
High-speed analog to digital converter (ADC) systems face challenges with instability in op amp sampling circuits, limited spurious free dynamic range (SFDR) and signal to noise ratio (SNR) due to capacitive loads, and high power consumption in pre-charge buffer approaches, especially in high-speed over-sampling and pipelined ADC systems.
Innovation Solution
The implementation of a system using a pre-charge capacitor and sampling capacitor configuration, where the pre-charge capacitor is charged during a non-sampling phase and decoupled during a fine sampling phase, allowing the operational amplifier to quickly settle the sampling capacitor for accurate sampling, reducing power requirements and improving SNR and SFDR.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If compensation capacitance is added to offset phase delay and enhance stability, then system stability is improved, but rise time increases and bandwidth is reduced
Solution Approach 1:
The patent segments the sampling operation into two distinct phases: a coarse sampling phase where the op amp drives the switching input load, and a fine sampling phase where a second op amp settles the holding capacitor. This segmentation allows each op amp to be optimized for its specific phase, avoiding the need for excessive compensation capacitance that would limit bandwidth.
Solution Approach 2:
The patent performs preliminary action by having the first op amp complete the coarse sampling and charge transfer before the second op amp begins the fine settling process. This preliminary action reduces the burden on the second op amp, allowing it to achieve high precision without requiring excessive compensation that would reduce bandwidth.
2Speed
If clock frequency and sampling capacitor size are increased to maintain over-sampling ratio, then bandwidth is improved, but settling time becomes insufficient and SFDR is limited
Solution Approach 1:
The patent divides the sampling process into coarse and fine phases, allowing the holding capacitor to be charged during the coarse phase and then settled to high precision during the fine phase. This segmentation provides sufficient settling time even at high clock frequencies, enabling both high bandwidth and high SFDR performance.
Solution Approach 2:
The patent introduces a second op amp as an intermediary that specifically handles the fine settling of the holding capacitor. This intermediary component bridges the gap between the coarse sampling operation and the final high-precision requirement, enabling accurate settling within the available time budget.
3Measurement precision
If a low pass RC filter is placed in the driver circuit to filter thermal noise, then SNR is improved, but settling time increases and high frequency signal attenuation occurs
Solution Approach 1:
The patent extracts the noise filtering function from the main signal path by using a switched capacitor filter that operates during the non-sampling phase. This allows thermal noise to be filtered without affecting the settling time during the sampling phase, as the filter is engaged only when the input is disconnected.
Solution Approach 2:
The patent employs periodic action by switching the RC filter into the signal path only during the non-sampling phase when the input is disconnected. During the sampling phase, the filter is bypassed to allow fast settling. This periodic engagement of the filter provides noise filtering without compromising settling time or bandwidth.
4Speed
If pre-charge buffer is added to provide initial surge current, then power consumption increases, but sampling speed is improved
Solution Approach 1:
The patent merges the pre-charge function with the main sampling operation by using the first op amp to perform both the coarse sampling and the initial charge transfer to the holding capacitor. This eliminates the need for a separate pre-charge buffer, reducing power consumption while maintaining sampling speed through the two-phase approach.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the SNR and SFDR performance while reducing power consumption, making it suitable for high-speed ADC systems and adaptable to various ADC types, particularly effective in CMOS technology.
Implementation Method 1
an operational amplifier operably coupled to a pre-charge capacitor for storing an input charge. A sampling capacitor is also coupled to the operational amplifier and to the pre-charge capacitor for receiving and holding the input charge
Data Source
AI summary
The invention provides methods and systems useful for quickly and accurately sampling a switched capacitive load. Systems are disclosed in which the methods are implemented using an operational amplifier operably coupled to a pre-charge capacitor for storing an input charge. A sampling capacitor is also coupled to the operational amplifier and to the pre-charge capacitor for receiving and holding the input charge. The system is so configured for a coarse sampling phase and a fine sampling phase the to ensure that the sampling capacitor settles quickly to provides an output.