ADC Sampling Circuit With Precharge for Low Input Charge
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Solution Overview
Problem
Conventional analog to digital converters (ADCs) face challenges in reducing input charge to sampling capacitors, leading to high power consumption and on-chip area usage, particularly with high sampling rates, especially when dealing with multiple analog input sources.
Innovation Solution
The proposed circuit design includes level shifting circuits and control signals to manage the charging and discharging of capacitive nodes, minimizing the input charge to the sampling capacitor by using transistors with controlled threshold voltage mismatches, thereby reducing current flow during the sampling process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If rail to rail buffers are used to sample the input voltage, then the input charge is eliminated and voltage drop across the input filter is reduced, but the on-chip area and power consumption increase significantly
Solution Approach 1:
The sampling capacitor is pre-charged to a voltage close to the input voltage before the actual sampling operation. This preliminary charging action reduces the charge that needs to be transferred during sampling, thereby reducing the current magnitude from the analog input node while maintaining high sampling rates
Solution Approach 2:
The circuit utilizes threshold voltage mismatches between transistors as a controllable parameter to regulate the charging process. By carefully selecting transistor threshold voltages, the sampling capacitor can be charged to a voltage close to the input voltage without requiring large current flows, thus reducing power consumption while maintaining sampling performance
2Speed
If rail to rail buffers are used to sample the input voltage, then the input charge is eliminated, but the on-chip area increases significantly
Solution Approach 1:
The sampling capacitor is pre-charged to a voltage close to the input voltage before the actual sampling operation. This preliminary charging action reduces the charge that needs to be transferred during sampling, thereby reducing the current magnitude from the analog input node while maintaining high sampling rates
Solution Approach 2:
The circuit utilizes threshold voltage mismatches between transistors as a controllable parameter to regulate the charging process. By carefully selecting transistor threshold voltages, the sampling capacitor can be charged to a voltage close to the input voltage without requiring large current flows, thus reducing power consumption while maintaining sampling performance
Data Source
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AI summary
An analog-to-digital converter (11) includes a sampling capacitor (C0) connected to a multiplexer output (OUT), discharge circuitry (N3) discharging the sampling capacitor (C0) during a first period beginning at a start of a sampling cycle, and level shifting circuitry (N1, P1, N0, P2, 13, R0, P3) charging the sampling capacitor (C0) to a voltage at a first analog input node (Nin) modified by a mismatch voltage resulting from mismatch in threshold voltages between a first transistor (P0) connected to the first analog input node (Nin) and a second transistor (N1) connected to the output node (OUT), during a second period beginning at expiration of the first period. A first switch (Sx) connects the first analog input node (Nin) to the output node (OUT) to charge the sampling capacitor (C0) to the voltage at the first analog input node (Nin), at expiration of the second period, and disconnects the first analog input node (Nin) from the output node (OUT) at an end of the sampling cycle of the analog-to-digital converter (11).