ADC Ramp Generator with Adjustable Shift for Reset-Free Conversion
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Solution Overview
Problem
Existing ramp analog-to-digital converters (ADCs) face slow conversion times and significant dead time due to the need for ramp reset operations, which become more pronounced with increasing resolution and the number of columns in image sensors, leading to inefficiencies and power consumption issues.
Innovation Solution
The proposed ADC circuit employs a ramp signal with linearly rising and falling portions and an adjustable shift at the reversal point, eliminating the need for ramp reset operations by maintaining the ramp signal at a constant level during the shift, thereby increasing resolution without time penalties and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If ramp reset operations are performed in state-of-the-art ADCs, then the ramp signal is reset to a well-defined value, but this causes significant dead time that increases with the number of columns and resolution
Solution Approach 1:
The patent applies continuity of useful action by eliminating the ramp reset dead time through a ramp generator that continuously generates the ramp signal without interruption. The ramp signal is generated in a continuous manner with linearly rising and falling portions, allowing the ADC to perform conversions without stopping to reset the ramp, thus maintaining continuous useful action and reducing conversion cycle time.
Solution Approach 2:
The patent applies dynamics by making the ramp signal dynamic with adjustable characteristics. The ramp generator produces a ramp signal with linearly rising and falling portions where the duration of the falling portion can be adjusted dynamically. This dynamic adjustment allows optimization of the ramp signal characteristics to achieve high resolution conversions without requiring fixed reset operations, thereby reducing dead time while maintaining measurement precision.
2Reliability
If the ramp load capacitance is increased to avoid kickback from comparator toggling, then the ramp signal stability is improved, but the ramp reset time becomes a larger fraction of the total conversion time
Solution Approach 1:
The patent applies continuity of useful action by designing a ramp generator that continuously charges the ramp load capacitance without interruption. The ramp signal is generated with a continuous charging phase followed by a controlled discharging phase, eliminating the need to stop and reset the capacitance. This continuous operation maintains ramp signal stability while improving conversion speed by eliminating reset dead time.
Solution Approach 2:
The patent applies periodic action through a ramp generator that operates in periodic cycles of linear rising and linear falling portions. The ramp signal alternates between charging (rising) and discharging (falling) phases in a periodic manner, with the falling portion duration being adjustable. This periodic operation allows the system to maintain stable ramp signal generation while optimizing the timing to reduce the fraction of time spent in reset operations, thereby improving productivity.
3Measurement precision
If two ramps are used for converting reference level and signal level, then both analog values are converted, but this doubles the conversion time compared to single ramp usage
Solution Approach 1:
The patent applies merging by combining the conversion of reference level and signal level into a single integrated conversion process. The ADC circuit is designed to accept both analog input signals and perform their conversion simultaneously or in an interleaved manner within one conversion cycle, using the continuous ramp signal. This merging eliminates the need for separate conversion cycles, thereby maintaining dual-level conversion accuracy while reducing the overall conversion cycle duration.
Solution Approach 2:
The patent applies preliminary action by preparing the ramp generator to continuously generate the ramp signal before conversion is needed. The ramp signal is pre-generated and continuously available, allowing the ADC to immediately begin converting both reference and signal levels without waiting for ramp initialization. This preliminary preparation of the ramp signal enables faster dual-level conversion by eliminating startup delays.
Data Source
AI summary
In one embodiment an analog-to-digital converter circuit has an input for receiving a first analog signal level and a second analog signal level, a ramp generator adapted to provide a ramp signal, a comparison unit coupled to the input and the ramp generator, a control unit coupled to the comparison unit the control unit having a counter, the control unit being prepared to enable the counter as a function of a comparison of the ramp signal with the first analog signal level and the second analog signal level, and an output for providing an output digital value as a function of a relationship between the first analog signal level and the second analog signal level. Therein the ramp signal has at least one linearly rising and at least one linearly falling portion and an adjustable shift at a reversal point between the rising and the falling portion of the ramp signal, the shift depending on the number of rising and falling portions of the ramp signal.