ADC Ramp Circuit Hold Scheme for RTN and Reference Noise
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Solution Overview
Problem
Analog-to-digital converters (ADCs) in sensors face issues such as increased noise, particularly Row Temporal Noise (RTN) and Vertical Fixed Pattern Noise (VFPN), which are exacerbated by the ADC design, and conventional solutions for addressing these noise types require high design effort and are not compatible with both digital and analogue Correlated Double Sampling (CDS) architectures.
Innovation Solution
A ramp circuit with a hold unit is introduced to maintain a constant reference voltage using a hold capacitor and semiconductor switches, allowing for hardware reuse and power savings by disabling the voltage reference source during non-sampling periods, and is compatible with both single-ended and differential ADC architectures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a voltage reference source is used to reset the ramp signal between subsequent samplings, then the ramp circuit can function properly, but noise increases
Solution Approach 1:
The hold unit pre-charges the hold capacitor to the reference voltage before the sampling operation begins. This preliminary action ensures that the ramp signal can be reset without needing to access the noisy voltage reference source during the critical sampling and resetting phases, thereby preventing noise injection into the signal path.
Solution Approach 2:
The hold capacitor acts as an intermediary between the voltage reference source and the ramp signal. It stores the reference voltage and provides a clean, noise-free reset voltage to the ramp signal during sampling operations, isolating the sensitive ramp circuit from the noisy reference source.
2Ease of operation
If the voltage reference source remains active during non-sampling periods, then the reference voltage is always available, but power consumption increases
Solution Approach 1:
The hold capacitor is pre-charged to the reference voltage before sampling operations begin. This preliminary charging action allows the voltage reference source to be switched off during non-sampling periods, as the hold capacitor maintains the necessary reference voltage level throughout the sampling and resetting operations without requiring continuous power from the reference source.
Solution Approach 2:
The voltage reference source operates periodically rather than continuously - it is activated only when the hold capacitor needs to be recharged (between frames or rows), and remains inactive during the sampling operations. This periodic operation significantly reduces average power consumption while ensuring reference voltage availability when needed.
3Device complexity
If a simple sample and hold circuit is used for short row times, then the circuit is simple, but leakage causes row FPN
Solution Approach 1:
The hold capacitor serves as an intermediary that isolates the sampling circuit from the effects of leakage. By storing the reference voltage on the hold capacitor and using it for resetting the ramp signal, the circuit avoids direct connection between the switching elements and the critical signal path during the hold period, thereby minimizing the impact of leakage currents on the output signal.
Solution Approach 2:
The invention extracts the reference voltage storage function into a separate hold capacitor that is decoupled from the main sampling switching circuit during the hold period. This separation removes the leakage paths from the critical signal path, as the hold capacitor is only connected to the ramp reset circuit and not directly to the sampling switches that generate FPN.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The ramp circuit effectively cancels RTN noise and reduces power consumption by minimizing reference noise, while being compatible with existing sensor architectures and enabling efficient use of CDS, achieving low area impact and power efficiency.
Implementation Method 1
a hold unit connected to the ramp unit and configured to hold a reference voltage for resetting the ramp signal between subsequent samplings of the analogue signal
Data Source
AI summary
Disclosed herein is a ramp circuit for an analogue to digital converter, ADC. The ramp circuit includes a ramp unit configured to provide a ramp signal usable for sampling an analogue signal. The ramp circuit also includes a hold unit connected to the ramp unit, the hold unit is configured to hold a reference voltage for resetting the ramp signal between subsequent samplings of the analogue signal.