Multi-Channel ADC Rate Allocation Without Round-Robin Sampling
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Solution Overview
Problem
Existing ADC systems face limitations in dynamically allocating data rates across multiple physical channels, leading to reduced data rates and introducing settling time errors and cross-talk due to round-robin sampling and rapid disconnection/reconnection.
Innovation Solution
A dynamically configurable ADC architecture using a set of N unit ADCs with common architecture, where control logic selects subsets with different data rates from an aggregate data rate, allowing for flexible trade-offs between sampling rate and number of physical channels without compromising ADC resolution, using a multi-phase clock and switch matrix for efficient data rate allocation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If round-robin sampling is used to allocate ADC data rate across multiple physical channels, then the ADC aggregate data rate can be distributed, but the data rate for any one channel is reduced and settling time errors and cross-talk are introduced
Solution Approach 1:
The ADC system is segmented into multiple independent unit ADCs, each capable of operating at full data rate. Instead of time-division multiplexing a single ADC, the patent divides the ADC functionality into parallel segments (unit ADCs) that can be independently activated. This allows selective engagement of multiple unit ADCs to achieve desired aggregate data rates without the resolution degradation caused by round-robin sampling.
Solution Approach 2:
Multiple unit ADCs are merged in parallel to achieve high aggregate data rates when needed. The control logic dynamically combines the output of selected unit ADCs based on the required data rate and number of physical channels. This merging approach maintains full resolution for each channel while providing flexible data rate allocation through parallel operation rather than sequential time-division multiplexing.
2Productivity
If rapid disconnection and reconnection is performed to connect ADC to each physical input for round-robin sampling, then data rate allocation is achieved, but settling time errors and cross-talk between channels are introduced
Solution Approach 1:
Multiple unit ADCs are pre-configured and ready to connect to different physical channels simultaneously. The control logic pre-establishes the connection topology before sampling begins, eliminating the need for rapid disconnection and reconnection during operation. Each unit ADC maintains a stable connection to its assigned channel, preventing settling time errors and cross-talk while still enabling flexible data rate allocation through selective activation of unit ADCs.
3Measurement precision
If multiple physical input channels are used for fine spatial resolution, then spatial sampling is improved, but ADC sampling rate per channel must be reduced
Solution Approach 1:
The system dynamically configures the number of active unit ADCs and their assignment to physical channels based on real-time requirements. When fine spatial resolution is needed, more unit ADCs are activated and assigned to different channels, each operating at full sampling rate. When spatial resolution is less critical, fewer unit ADCs are activated to reduce power consumption. This dynamic reconfiguration allows the system to optimize the trade-off between spatial resolution and power efficiency while maintaining high sampling rates on active channels.
4Measurement precision
If high ADC sampling rate is used on fewer physical channels for high range resolution, then range resolution is improved, but spatial sampling becomes coarser and system cost, power and complexity increase
Solution Approach 1:
The same set of unit ADCs serves multiple functions depending on configuration. When high range resolution is needed, fewer unit ADCs are activated with high sampling rates. When fine spatial resolution is needed, more unit ADCs are activated with lower sampling rates. The control logic provides universal functionality to support different operational modes without requiring separate dedicated hardware for each function, thereby reducing overall system complexity while maintaining the ability to achieve high performance in either spatial or range resolution based on application requirements.
Data Source
AI summary
An integrated circuit includes a set of N unit analog-to-digital converters (ADCs) having a common architecture, and which provide an aggregate data rate. Moreover, the integrated circuit includes control logic that selects subsets of the set of N unit ADCs in order to realize sub-ADCs of different data rates that can each be an arbitrary integer multiple of an inverse of N times the aggregate data rate of the N unit ADCs. Furthermore, the control logic may dynamically select the subsets on the fly or on a frame-by-frame basis. This dynamically selection may occur at boot time and/or a runtime. Additionally, the given different data rate may correspond to one or more phases of a multi-phase clock in the integrated circuit, where the multiphase clock may include a number of phases corresponding to a number of possible subsets, and given selected subsets may not use all of the available phases.