ADC Result Register Readout Counter for Continuous Sampling
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Solution Overview
Problem
Existing gate driver systems rely solely on triggering points of switching signals for data sampling, which limits the accuracy of monitored system states and fails to generate data samples when the switching signal stops, such as during vehicle stoppages.
Innovation Solution
The system employs both switching and timing signals to control analog-to-digital converters (ADCs), allowing continuous data sampling even when the switching signal is inactive, and uses a readout counter value to validate data samples, reducing computational burden.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the system relies only on triggering points of switching signals for data sampling, then the device complexity is reduced, but the measurement precision and reliability of system state monitoring deteriorate
Solution Approach 1:
The patent combines two data sampling mechanisms: switching signal-triggered sampling and free-running counter-triggered sampling. The free-running counter operates independently of the switching signal, ensuring continuous sampling even when the switching signal stops. This merging of sampling sources resolves the contradiction by maintaining measurement precision without significantly increasing device complexity, as the counter mechanism is integrated into the existing data acquisition architecture.
Solution Approach 2:
The patent introduces a free-running counter as an intermediary mechanism between the system clock and the data sampling process. This counter acts as a mediator that generates sampling triggers independently of the switching signal, ensuring that data collection continues during signal cessation. The intermediary counter maintains measurement precision without requiring direct coupling to the switching signal, thus resolving the contradiction between simplicity and accuracy.
2Ease of operation
If the system uses only switching signal triggering for ADC sampling, then the ease of operation is maintained, but the productivity of data collection deteriorates when switching signal stops
Solution Approach 1:
The patent implements a dynamic sampling system that adapts its operation mode based on the presence of switching signals. When switching signals are active, the system operates in switching-triggered mode for synchronized sampling. When switching signals cease, the system automatically transitions to free-running counter mode, maintaining data collection productivity. This dynamic adaptation resolves the contradiction by preserving ease of operation while ensuring continuous high-productivity data collection.
Solution Approach 2:
The patent ensures continuous data collection by implementing a free-running counter that operates without interruption regardless of switching signal status. The counter continuously generates sampling triggers, maintaining the productivity of data collection even when the switching signal stops. This continuity of useful action resolves the contradiction between ease of operation and data collection productivity during signal cessation.
3Measurement precision
If the system compares time stamps to validate data, then the measurement precision is maintained, but the computational burden increases
Solution Approach 1:
The patent replaces complex time stamp comparison validation with a simple readout counter value that can be quickly checked. The readout counter provides a lightweight, computationally inexpensive validation mechanism that maintains data precision by verifying data recency without requiring heavy computational resources. This substitution resolves the contradiction by maintaining measurement precision while dramatically reducing computational burden.
Data Source
AI summary
A circuit includes one or more datastores configured to store a result register and a readout counter value and logic circuitry coupled to the one or more datastores. The logic circuitry is configured to cause, for a cycle of a plurality of cycles of a periodic signal, one or more analog-to-digital converters (ADCs) to store data to the result register and modify the readout counter value in response to the one or more ADCs storing the data to the result register for the cycle. In response to a read request for the data at the result register for the cycle, the logic circuitry is configured to output the data stored by the result register, output the readout counter value for the cycle, and, after the output of the readout counter value, set the readout counter value to a predetermined value.