Successive Half-Scale ADC Reference Accumulation for High Resolution
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional analog-to-digital converters (ADCs) face challenges in achieving high resolution with small area requirements, as increasing resolution in folding and interpolating ADCs leads to non-linearity, while flash ADCs require a large area and pipeline ADCs are slower and less efficient in area usage.
Innovation Solution
The proposed ADC structure includes a ½ powered voltage generator that successively divides a full-scale voltage by 2, an accumulator that updates the reference voltage based on the current divided voltage and output bit, and a comparator that compares the updated reference voltage with the input signal to generate output bits, reducing area requirements and increasing resolution without using a separate digital-to-analog converter.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the folding factor is increased to increase resolution in folding and interpolating ADCs, then resolution is improved, but non-linearity increases
Solution Approach 1:
The ADC conversion process is segmented into multiple stages with different folding factors. Instead of using a single high folding factor, the patent divides the conversion into cascaded stages (e.g., first stage with folding factor 2, second stage with folding factor 4), where each stage handles a portion of the resolution requirement. This segmentation allows achieving high overall resolution while maintaining low non-linearity in each individual stage.
2Measurement precision
If flash ADC structure is used to achieve high resolution, then resolution is improved, but area increases significantly
Solution Approach 1:
The flash ADC structure is segmented into multiple cascaded stages, each with fewer comparators. Instead of implementing all N bits in a single flash stage requiring 2^N-1 comparators, the patent divides the conversion into stages (e.g., first stage converts to intermediate bits, second stage refines to final bits), dramatically reducing the number of comparators needed in each stage while achieving the same overall resolution.
Solution Approach 2:
The first conversion stage performs a preliminary conversion to generate intermediate digital bits that approximate the input signal. This preliminary action reduces the dynamic range for the subsequent stage, allowing the second stage to focus on refining the remaining resolution with fewer comparators, thereby reducing total area while maintaining high resolution.
3Area of stationary object
If pipeline ADC structure is used to reduce area, then area is reduced, but speed decreases
Solution Approach 1:
The patent merges the advantages of flash ADC (high speed) and pipeline ADC (small area) by combining elements of both architectures. The cascaded folding structure uses flash-like comparator arrays in each stage for high-speed comparison while organizing them in a pipeline-like cascaded configuration that reduces total area. Each stage operates independently and quickly, maintaining high overall conversion speed.
Data Source
AI summary
An analog-to-digital converter includes a ½ powered signal generator configured to generate divided signals by successively dividing a full scale signal by 2 and output one of the divided signals, an accumulator configured to update a reference signal according to a current divided signal and a current output bit, and a comparator configured to compare the updated reference signal with an input signal and generate a next output bit.