Differential ADC Reference Control for Low-Power Capacitor Switching
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Solution Overview
Problem
The power consumption of analog-to-digital converters (ADCs), particularly in devices with semiconductors, has not decreased at the same rate as the reduction in semiconductor size and power consumption, with a significant portion attributed to the power consumption of ADCs, especially in types like Flash-ADC and level-crossing ADCs, due to frequent comparisons with reference signals.
Innovation Solution
An ADC design utilizing signed binary values to control digital-to-analog converters (DACs) with capacitor banks, where capacitors are controlled by bits of a digital reference signal, reducing the need for switching of more significant bits by adjusting the reference signal to approximate the input signal difference, and employing an LSB-first approach for sparse signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional ADC architectures (Flash-ADC, level-crossing ADC) are used to achieve fast conversion, then conversion speed is improved, but power consumption increases significantly
Solution Approach 1:
The patent divides the reference signal into multiple segments corresponding to different bit positions (MSB to LSB). The capacitor bank is segmented into groups, where each group handles specific bit comparisons. This segmentation allows the ADC to perform comparisons in stages rather than all at once, reducing the simultaneous switching activity and thus lowering power consumption while maintaining conversion speed.
Solution Approach 2:
The patent performs preliminary comparisons starting from the most significant bit (MSB) before proceeding to less significant bits. By determining the MSB first and fixing it, subsequent comparisons only need to resolve remaining bits, significantly reducing the number of comparison operations required. This preliminary action approach minimizes the total switching activity in the capacitor bank, thereby reducing power consumption.
2Measurement precision
If frequent comparisons with reference signals are performed to achieve accurate conversion, then measurement precision is improved, but power consumption increases
Solution Approach 1:
The patent performs preliminary comparisons starting from the most significant bit (MSB) before proceeding to less significant bits. By determining the MSB first and fixing it, subsequent comparisons only need to resolve remaining bits, significantly reducing the number of comparison operations required. This preliminary action approach minimizes the total switching activity in the capacitor bank, thereby reducing power consumption.
Solution Approach 2:
The patent dynamically adjusts the reference signal levels based on the results of previous comparisons. After each comparison stage, the reference signal is updated to reflect the determined bit values, allowing subsequent comparisons to operate with optimized reference levels. This dynamic adaptation reduces unnecessary switching activity and minimizes power consumption while maintaining conversion accuracy.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method significantly reduces power consumption by minimizing the switching of capacitors, especially for sparse signals, making the ADC more power efficient and suitable for devices with reduced power demands.
Implementation Method 1
a first capacitor bank having N number of first capacitors, wherein first plates of the first capacitors of the N number of first capacitors are controlled by bits of a first digital reference signal
Data Source
AI summary
An analog-to-digital converter, ADC, is provided. The ADC comprises a comparator having a first input and a second input. The ADC further comprises a first digital-to-analog converter, DAC, and a second DAC configured to receive a first and a second digital reference signal, respectively. The digital reference signals (Dref) represent a signed binary value. The ADC is configured to compare input voltages (Vin), based on a first sampled input signal of a differential input signal and the first digital reference signal, and based on a second sampled input signal of the differential input signal and the second digital reference signal and, based on said comparison, adjust the reference voltage so as to approximate the differential input signal.