ADC Reference Network With Low-Impedance Constant-Current Output
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Solution Overview
Problem
Pipelined analog-to-digital converter systems face challenges in generating accurate low-impedance reference signals, which are critical for high-speed and high-resolution signal processing, as errors in these signals can corrupt the final digital output and are sensitive to temperature, process, and supply variations.
Innovation Solution
The implementation of a reference network using a complementary common-drain output stage and diode-coupled transistors, along with controllers to manage the output reference voltage and current, ensures low impedance and stability of reference signals, making them independent of temperature and supply variations while enhancing response speed and efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional reference signal generation methods are used, then the system can operate, but the reference signals have high impedance and are sensitive to temperature, process, and supply variations
Solution Approach 1:
The patent introduces an intermediate buffer stage between the reference voltage source and the output nodes. This buffer stage acts as a mediator that isolates the reference signals from load variations and external disturbances, thereby reducing sensitivity to temperature, process, and supply variations while maintaining signal stability.
Solution Approach 2:
The reference signal generation circuit uses a composite structure combining multiple transistor types (PMOS and NMOS) in a complementary configuration. This composite approach creates a push-pull output stage that can simultaneously source and sink current, reducing output impedance and improving signal stability against various disturbances.
2Reliability
If the reference network is designed for high accuracy, then the reference signals are stable, but the response speed decreases
Solution Approach 1:
The patent implements a dynamic reference signal generation system where the buffer stage can rapidly switch between different output states. The complementary transistor configuration allows the circuit to dynamically respond to changing load conditions and clock signals, achieving both high accuracy through proper biasing and fast response through low output impedance.
Solution Approach 2:
The reference network utilizes parameter optimization in the transistor sizing and biasing conditions. By carefully selecting transistor width-to-length ratios and bias currents, the design achieves an optimal balance between output impedance (for accuracy) and bandwidth (for speed), allowing the system to maintain high reference signal accuracy while responding quickly to signal processing requirements.
3Speed
If the reference network provides low impedance output, then the reference signals are fast and accurate, but the power consumption increases
Solution Approach 1:
The reference signal generation is synchronized with the clock signal, operating in a periodic manner that matches the signal processing requirements. The buffer stage is activated only when reference signals are needed, and the complementary transistor configuration allows for efficient switching that minimizes power consumption during transitions while maintaining low output impedance during active periods.
Solution Approach 2:
The patent employs parameter optimization in the biasing conditions and transistor dimensions to achieve the lowest possible power consumption for a given output impedance requirement. By carefully adjusting the bias currents and transistor sizes, the design finds the optimal operating point where power efficiency and speed performance are balanced, avoiding excessive power dissipation while maintaining fast response characteristics.
Data Source
AI summary
Reference network embodiments are provided for use in pipelined signal converter systems. The network embodiments are fast and power efficient and they generate low-impedance reference signals through the use of a complimentary common-drain output stage, at least one diode-coupled transistor inserted between transistors of the output stage, and a controller. The controller is configured to provide a backgate voltage to the diode-coupled transistor to thereby establish a substantially-constant output current. The controller is further configured to provide gate voltages to the output stage to establish top and bottom reference voltages about the diode-coupled transistor that are spaced from a common-mode voltage. This reference structure maintains a constant output current as the span between the top and bottom reference voltages is selectively altered. In different embodiments, the diode-coupled transistor is replaced with a bipolar junction transistor.