ADC Reference Voltage Settling With Pre-Charged Capacitors

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

In high-speed analog-to-digital converter (ADC) systems, the reference voltage (VREF) takes too long to settle, leading to distortion in bit conversions and reduced overall ADC performance. This issue is exacerbated in time-interleaved ADC arrangements due to crosstalk and shared reference voltage challenges.

Innovation Solution

The implementation of a capacitor bank and a fast recharge circuit within the ADC, which includes pre-charged capacitors synchronized by a controller to match current impulses with the ADC's current draw, thereby minimizing VREF drops and improving settling speed.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If a conventional ADC design is used without additional settling circuits, then the device complexity is low, but the reference voltage settling time is too long causing distortion in bit conversions

Engineering Contradiction:

Improvereference voltage settling timeVSAvoiddevice complexity

Core Design Contradiction:

Loss of timeVSDevice complexity

Solution Approach 1:

The patent pre-charges capacitors connected to the reference voltage line before the ADC conversion process begins. This preliminary action ensures that the reference voltage is already stabilized and ready, eliminating delays during the actual conversion and achieving fast settling without adding complex active buffer circuits

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent extracts and removes the need for active buffer circuits by using a passive capacitor-based approach. By taking out the active buffering component and replacing it with pre-charged capacitors, the design achieves fast reference voltage settling while reducing device complexity and power consumption

Inventive Principle:

Principle #2Taking out (Extraction)

2Speed

If active buffer circuits are used to speed up reference voltage settling, then the settling speed improves, but the power consumption and area requirements increase

Engineering Contradiction:

Improvereference voltage settling speedVSAvoidpower consumption

Core Design Contradiction:

SpeedVSUse of energy by moving object

Solution Approach 1:

The patent uses simple passive capacitors instead of expensive and power-hungry active buffer circuits. These capacitors are pre-charged and then used temporarily during the conversion process to maintain reference voltage, achieving fast settling speed with minimal power consumption and small area

Inventive Principle:

Principle #27Cheap short-living objects (Disposable)

Solution Approach 2:

The patent employs periodic pre-charging of capacitors synchronized with the ADC conversion cycles. This periodic action ensures the reference voltage is refreshed and maintained at the appropriate level throughout the conversion process, achieving consistent fast settling speed without continuous power consumption

Inventive Principle:

Principle #19Periodic action

3Productivity

If time-interleaved ADC arrangements are used to increase conversion rate, then the productivity improves, but crosstalk between channels deteriorates performance

Engineering Contradiction:

Improveconversion rateVSAvoidcrosstalk

Core Design Contradiction:

ProductivityVSObject-affected harmful factors

Solution Approach 1:

The patent divides the time-interleaved ADC system into separate capacitor banks for each ADC channel. Each channel has its own dedicated pre-charged capacitors, which isolates the reference voltage lines and eliminates crosstalk between channels while maintaining high conversion rates

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent applies different capacitor values and pre-charge voltages to different positions in the time-interleaved array based on their specific requirements. This local optimization ensures each channel receives the appropriate reference voltage characteristics, minimizing crosstalk and maximizing overall system performance

Inventive Principle:

Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach reduces power and area requirements by minimizing active buffer needs, allows for faster conversion rates at higher resolutions, and effectively mitigates crosstalk in time-interleaved ADC arrangements, ensuring accurate and rapid reference voltage settling.

Implementation Method 1

connecting, at the time that the digital-to-analog converter generates the analog reference voltage, a pre-charged capacitor on the reference voltage line

Methodology Applied

Scientific EffectCapacitance: Capacitance

Data Source

PatentUS20250030432A1Analog-to-digital converters and methods for settling of the reference voltage in analog-to-digital converters

Publication Date: 2025.01.23 INTEL CORP

AI summary

Disclosed herein are devices, methods, and systems related to analog-to-digital converters (ADCs), and in particular, to settling the reference voltage in an ADC and to settling the reference voltage in a time-interleaved arrangement of ADCs. A method of settling of a reference voltage in an ADC may include generating, on a reference voltage line, an analog reference voltage, and connecting, at the time of generating the analog reference voltage, a pre-charged capacitor of the ADC to the reference voltage line to reduce a voltage error during the generation of the analog reference voltage.