Subranging ADC Reference Precharging for Faster Ladder Settling
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Solution Overview
Problem
Conventional two-step subranging ADC architectures face a speed bottleneck due to the settling time required for reference ladders, especially at higher sampling rates, as the time allocated for reference settling decreases with increasing conversion speed, affecting the accuracy and efficiency of analog-to-digital conversion.
Innovation Solution
The proposed solution involves a precharging mechanism where the input line is set to the input voltage before switching to the coarse reference, allowing the voltage to settle more quickly, and using separate coarse and fine reference ladders to optimize settling times and reduce loading effects, thereby extending the time available for reference settling and improving conversion speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the sampling rate is increased to improve conversion speed, then the ADC can process signals faster, but the time allocated for reference settling decreases, causing settling time insufficiency and affecting conversion accuracy
Solution Approach 1:
The patent pre-charges the input line to the input voltage level before the switching event occurs. This preliminary action ensures that when the switch transitions from the input voltage to the coarse reference voltage, the voltage difference to be settled is minimized, thereby reducing the settling time requirement and enabling faster conversion rates without sacrificing accuracy
2Device complexity
If a single reference ladder is used to simplify the architecture, then the device complexity is reduced, but the settling time increases due to large loading from multiple switches and comparators
Solution Approach 1:
The patent divides the reference ladder into two separate structures: a coarse reference ladder and a fine reference ladder. The coarse reference ladder handles the initial voltage switching with minimal loading, while the fine reference ladder handles the subsequent fine-tuning. This segmentation reduces the loading on each individual reference ladder, thereby reducing the settling time for both while maintaining architectural simplicity
3Measurement precision
If the number of switches and comparators in the reference ladder is increased to improve resolution, then the ADC accuracy is enhanced, but the loading on the reference ladder increases, causing settling time to become a speed bottleneck
Solution Approach 1:
The patent segments the comparison process into two stages: coarse comparison using the coarse reference ladder and fine comparison using the fine reference ladder. This segmentation allows the use of multiple switches and comparators in each stage without overwhelming the loading on a single reference ladder, thereby maintaining high resolution while reducing the overall settling time and eliminating the speed bottleneck
Solution Approach 2:
The coarse reference ladder performs a preliminary comparison to establish a coarse voltage level before the fine reference ladder performs the precise comparison. This preliminary action reduces the voltage swing required in the fine reference ladder, thereby reducing its settling time and allowing for more comparators and switches to be used without creating a speed bottleneck
Data Source
AI summary
A coarse reference ladder provides a plurality of coarse references. A coarse ADC receives an input voltage. The coarse ADC performs a first comparison of the input voltage and the plurality of coarse references and outputs a coarse output. A switch matrix is configured to close a switch based on the coarse output. An input line corresponding to a coarse reference is coupled to the switch matrix. The input line is precharged to the input voltage. The input line settles from the precharged input voltage to the coarse reference. A fine reference ladder provides a plurality of fine references based on the coarse reference. A fine ADC receives the input voltage and performs a second comparison of the input voltage and the plurality of fine references and outputs a fine output. Logic outputs a digital output for the input voltage based on the coarse output and the fine output.