Interleaved ADC Reference Replica Calibration for Gain Mismatch
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Solution Overview
Problem
Time-interleaved analog-to-digital converters (ADCs) face challenges in achieving full resolution due to mismatch errors caused by process, voltage, and temperature variations, which degrade performance and dynamic range, and existing correction methods either fail to address non-reference-related mismatches or amplify noise.
Innovation Solution
An integrated circuit with a full-scale reference generation circuit that includes analog circuits and digital-to-analog converters to generate variable currents for full-scale corrections, using open-loop buffers and a calibration engine to adjust and match the gains of interleaved ADCs, reducing the impact of mismatch errors and noise amplification.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If digital post-processing is used to correct mismatch errors, then gain matching between ADCs is improved, but noise is amplified
Solution Approach 1:
The patent introduces a full-scale reference voltage as an intermediary standard against which all ADCs are calibrated. This reference voltage serves as a common mediator that enables direct comparison and adjustment of ADC gains without requiring complex digital post-processing between ADC pairs, thereby avoiding noise amplification while achieving precise gain matching.
Solution Approach 2:
The patent implements a feedback mechanism where the full-scale reference voltage is used to monitor and adjust the gain of each ADC. By continuously comparing ADC outputs against the reference and applying corrective feedback, the system achieves accurate gain matching through controlled adjustment rather than noisy digital correction.
2Stability of the object's composition
If a common full-scale reference is used for multiple ADCs, then reference-related consistency is improved, but non-reference-related mismatch errors remain and noise is coupled among ADCs
Solution Approach 1:
The patent segments the reference system by providing individual full-scale reference voltages to each ADC rather than sharing a single common reference. This segmentation allows each ADC to be independently calibrated against its own reference copy, preventing noise coupling while still maintaining reference consistency through replicated reference generation.
Solution Approach 2:
The patent applies local quality by tailoring the reference voltage delivery to each individual ADC's specific needs. Each ADC receives a full-scale reference voltage that is locally optimized for its particular characteristics and operating conditions, allowing independent correction of non-reference-related mismatch errors while maintaining overall system consistency.
3Productivity
If multiple ADCs are operated in parallel to increase sampling rate, then productivity is improved, but mismatch errors due to process, voltage and temperature variations degrade performance
Solution Approach 1:
The patent applies preliminary action by calibrating each ADC against the full-scale reference voltage before normal operation begins. This pre-calibration establishes accurate gain settings for all ADCs in the parallel array, ensuring that when the high-speed parallel conversion begins, all converters are already properly matched and will maintain consistent performance throughout operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution improves the matching of gain and full-scale voltages across interleaved ADCs, enhancing their performance by correcting for random transistor mismatch and gradient errors without amplifying noise, thus improving the overall performance of the ADC system.
Implementation Method 1
a full-scale reference generation circuit that includes an analog circuit, where the analog circuit generates full-scale reference voltages of full scales of each ADC in the set of interleaved ADCs
Implementation Method 2
the full-scale reference generation circuit may include digital-to-analog converters (DACs) that provide variable currents that, at least in part, specify the full-scale reference voltages
Implementation Method 3
the full-scale reference generator circuits include open-loop buffers
Data Source
AI summary
An integrated circuit may include a full-scale reference generation circuit that corrects for variation in the gain or full scale of a set of interleaved analog-to-digital converters (ADCs). Notably, the full-scale reference generation circuit may provide a given full-scale or reference setting for a given interleaved ADC, where the given full-scale setting corresponds to a predefined or fixed component and a variable component (which may specify a given full-scale correction for a given full scale). For example, the full-scale reference generation circuit may include a full-scale reference generator replica circuit that outputs a fixed current corresponding to the fixed component. Furthermore, the full-scale reference generation circuit may include a full-scale reference generator circuit that outputs a first voltage corresponding to the given full-scale setting based at least in part on the fixed current and a variable current that, at least in part, specifies the given full-scale correction.