ADC Reference Voltage Circuit with Two-Phase DAC Charging
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Solution Overview
Problem
Existing high-precision analog-to-digital converters face challenges in achieving high Spurious Free Dynamic Range (SFDR) due to the large layout area and power consumption of the reference voltage portion, which is necessary for accurate voltage control in capacitor arrays.
Innovation Solution
A reference voltage controlling circuit that includes a reference voltage generating circuit and a logic controlling circuit, utilizing multiple switching units to manage the charging and discharging of DAC capacitor arrays with multiple reference voltages, allowing for a two-phase charging process that maintains stability and accuracy without increasing decoupling capacitance or driving current, thereby reducing layout area and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a large decoupling capacitor and large reference voltage driving current are used to achieve high SFDR performance, then the SFDR performance is improved, but the layout area and power consumption increase significantly
Solution Approach 1:
The patent divides the reference voltage generation into two separate circuits: a first reference voltage generating circuit and a second reference voltage generating circuit. Each circuit has its own decoupling capacitor and driving current source. This segmentation allows the total decoupling capacitance and driving current to be distributed, reducing the area and power consumption of any single reference voltage portion while maintaining the overall SFDR performance requirement.
2Measurement precision
If a large decoupling capacitor and large reference voltage driving current are used to achieve high SFDR performance, then the SFDR performance is improved, but the power consumption increases
Solution Approach 1:
The patent divides the reference voltage generation into two separate circuits: a first reference voltage generating circuit and a second reference voltage generating circuit. Each circuit has its own decoupling capacitor and driving current source. This segmentation allows the total decoupling capacitance and driving current to be distributed, reducing the area and power consumption of any single reference voltage portion while maintaining the overall SFDR performance requirement.
3Area of stationary object
If the reference voltage portion is reduced to decrease layout area, then the layout area is reduced, but the SFDR performance deteriorates
Solution Approach 1:
The patent divides the reference voltage generation into two separate circuits: a first reference voltage generating circuit and a second reference voltage generating circuit. Each circuit has its own decoupling capacitor and driving current source. This segmentation allows the total decoupling capacitance and driving current to be distributed, reducing the area and power consumption of any single reference voltage portion while maintaining the overall SFDR performance requirement.
Solution Approach 2:
The patent employs a two-phase charging process controlled by a logic controlling circuit. The first reference voltage is applied during a first phase, and the second reference voltage is applied during a second phase. This periodic switching allows the capacitor array to be charged efficiently without requiring excessively large reference voltage portions, thereby maintaining SFDR performance while reducing area.
4Measurement precision
If a two-phase charging process with multiple reference voltages is implemented, then the charging stability and accuracy are improved, but the device complexity increases
Solution Approach 1:
The patent divides the reference voltage generation into two separate circuits: a first reference voltage generating circuit and a second reference voltage generating circuit. Each circuit has its own decoupling capacitor and driving current source. This segmentation allows the total decoupling capacitance and driving current to be distributed, reducing the area and power consumption of any single reference voltage portion while maintaining the overall SFDR performance requirement.
Solution Approach 2:
The patent employs a two-phase charging process controlled by a logic controlling circuit. The first reference voltage is applied during a first phase, and the second reference voltage is applied during a second phase. This periodic switching allows the capacitor array to be charged efficiently without requiring excessively large reference voltage portions, thereby maintaining SFDR performance while reducing area.
Data Source
AI summary
A reference voltage controlling circuit and an analog-to-digital converter are disclosed. The reference voltage controlling circuit includes a reference voltage generating circuit, a plurality of groups of sampling switching units and a logic controlling circuit. The DAC capacitor array switches the sampling switching units to a second positive reference voltage and a second negative reference voltage before starting sampling or conversion, and is charged and discharged with the second positive reference voltage and the second negative reference voltage to raise a voltage to a preset voltage. The sampling switching unit is switched to a first positive reference voltage and a first negative reference voltage to charge and discharge the DAC capacitor array to a target voltage. The rising of the voltage from the preset voltage to the target voltage is completed by the first positive reference voltage and the first negative reference voltage.