ADC Register Sequencing for Mixed-Rate Conversion Results

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Solution Overview

Problem

Existing ADC circuitry fails to provide a single set of registers that can both deliver conversion results as soon as they are generated for sensing and control applications and buffer high-frequency conversion results for signal processing applications, leading to increased memory requirements and computational expense.

Innovation Solution

The implementation of a configurable ADC circuitry with sequencer circuitry that determines the conversion mode and uses a First In First Out (FIFO) mode to store and transfer digital values, allowing for single-channel and multi-channel sensing and control, as well as single-channel and multi-channel signal processing operations, using a single set of result registers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If separate sets of registers are used for sensing/control applications and signal processing applications, then both application types can be supported simultaneously, but memory requirements and device complexity increase

Engineering Contradiction:

Improvesupport for multiple application typesVSAvoidmemory requirements

Core Design Contradiction:

Adaptability or versatilityVSQuantity of substance

Solution Approach 1:

The patent implements a single set of result registers that serves multiple purposes: storing conversion results for both sensing/control applications and signal processing applications. The sequencer circuitry dynamically determines whether to operate in single transfer state or multiple transfer state based on the application type, allowing the same hardware resources to be efficiently shared between different application domains without requiring separate register sets

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The system employs dynamic state determination where the sequencer circuitry automatically switches between single transfer state (for sensing/control) and multiple transfer state (for signal processing) based on real-time application requirements. This dynamic adaptation allows optimal use of the single register set for different operational modes, resolving the contradiction between versatility and memory efficiency

Inventive Principle:

Principle #15Dynamics

2Adaptability or versatility

Engineering Contradiction:

Improvesupport for multiple application typesVSAvoidcomputational expense

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The sequencer circuitry is designed to handle both sensing/control and signal processing operations through a unified control mechanism. By implementing a single set of control registers and result registers that can be configured for different application types, the system reduces device complexity while maintaining versatility. The sequencer dynamically selects the appropriate transfer state based on application requirements, eliminating the need for separate control paths for different application domains

Inventive Principle:

Principle #6Universality (Multi-functionality)

3Quantity of substance

If a single set of registers is used for both sensing/control and signal processing applications, then memory usage is minimized, but the ability to handle high-frequency conversions is reduced

Engineering Contradiction:

Improvememory usageVSAvoidconversion rate

Core Design Contradiction:

Quantity of substanceVSProductivity

Solution Approach 1:

The system dynamically adjusts its operational state based on the application type. For signal processing applications requiring high conversion rates, the sequencer enters multiple transfer state where it efficiently manages data flow to and from the single result register set. For sensing/control applications with lower rates, single transfer state is used. This dynamic state management allows the system to maximize productivity for high-frequency applications while maintaining efficient memory usage through the shared register set

Inventive Principle:

Principle #15Dynamics

4Reliability

If application-specific register sets are implemented, then optimized performance for specific applications is achieved, but DMA bus utilization efficiency decreases

Engineering Contradiction:

Improveapplication-specific performanceVSAvoidDMA bus utilization

Core Design Contradiction:

ReliabilityVSLoss of energy

Solution Approach 1:

The sequencer circuitry ensures continuous and efficient DMA bus utilization by dynamically managing data transfers based on application requirements. The single set of registers serves as a unified buffer that maintains continuous data flow for both sensing/control and signal processing applications. By avoiding separate register sets and their associated separate DMA transfer paths, the system maximizes DMA bus utilization efficiency while maintaining application-specific performance optimization through intelligent transfer state management

Inventive Principle:

Principle #20Continuity of useful action

Data Source

PatentUS11942962B2Methods and apparatus to write data to registers

Publication Date: 2024.03.26 TEXAS INSTRUMENTS INC

AI summary

Methods, apparatus, systems, and articles of manufacture are disclosed. An example apparatus includes interface circuitry to receive an analog signal. The example apparatus also includes sequencer circuitry to: determine whether the apparatus is to operate in a single transfer state or a multiple transfer state; access a configuration from a control register in a plurality of control registers; initiate a conversion of the analog signal to a digital value based on the configuration; and write the digital value to a result register in a plurality of result registers based on the determination.