Analog-Digital Converter With Repeated Comparison For High Gain
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Solution Overview
Problem
Conventional analog-digital converters in image sensors face challenges in increasing analog gain without increasing circuit area and power consumption, and reducing the ramp signal range degrades the signal-to-noise ratio (SNR).
Innovation Solution
The proposed solution involves an analog-digital converter that repeats the comparison of an input signal to a ramp signal corresponding to the analog gain, performs counting operations based on the comparison signal, and limits the counted bits to maintain the ramp signal range and clock speed, while discarding overflows to enhance analog gain without degrading other analog characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a separate pre-amplifier is added to increase analog gain, then the analog gain is improved, but the circuit area and power consumption increase
Solution Approach 1:
The patent merges the pre-amplifier function with the existing analog-digital converter circuit by using the same comparator and counter resources. The comparator compares the pixel signal with a ramp signal, and the counter counts the comparison results, effectively integrating amplification and conversion functions into a unified circuit structure that shares common components.
Solution Approach 2:
The analog-digital converter is designed to perform multiple functions: it acts as both a signal amplifier and a digital converter. The comparator and counter units serve dual purposes, enabling the circuit to achieve pre-amplification while simultaneously performing analog-to-digital conversion, thereby eliminating the need for separate dedicated pre-amplifier circuits.
2Reliability
If the range of a ramp signal is reduced to increase analog gain, then the analog gain is improved, but the signal to noise ratio is degraded
Solution Approach 1:
The patent employs periodic ramp signals that repeat over multiple cycles, with each cycle corresponding to a specific gain level. The comparator performs repeated comparisons during each ramp cycle, and the counter accumulates comparison results across multiple periods. This periodic operation allows the system to achieve high effective gain through temporal integration while maintaining adequate signal levels throughout the conversion process.
Solution Approach 2:
The analog-digital conversion process maintains continuous useful action by keeping the comparator and counter operating throughout the entire conversion period. The ramp signal continuously sweeps through its range, and the counter continuously accumulates comparison results, ensuring that the amplification and conversion processes occur without interruption, thereby preserving signal integrity and noise characteristics.
3Reliability
If the range of a ramp signal is reduced to increase analog gain, then the analog gain is improved, but the level of the ramp signal is lowered making it vulnerable to noise
Solution Approach 1:
The system uses periodic ramp signals that maintain adequate voltage levels throughout their cycle while repeating multiple times to achieve the desired effective gain. Each ramp cycle operates at a safe signal level that is not vulnerable to noise, and the cumulative effect of multiple cycles provides the necessary amplification without ever exposing the signal to noise-sensitive conditions.
Solution Approach 2:
The comparator acts as an intermediary that protects the ramp signal from noise vulnerability. By comparing the pixel signal against the ramp signal in a controlled manner and using the counter to accumulate results, the system mediates the conversion process in a way that maintains adequate signal levels throughout, preventing direct exposure of low-level signals to noise without requiring actual signal amplification.
Data Source
AI summary
An analog-digital converter may include a comparator suitable for comparing an input signal to a ramp signal to repetitively output a comparison signal a number of times corresponding to an analog gain for an analog-digital conversion; a counter receiving the repetitively outputted comparison signal from the comparator, the counter being suitable for performing a counting operation based on the repetitively outputted comparison signal; and a counting limiter suitable for limiting the counted number of bits by a maximum counted bit number of the counter.