Capacitor-Array ADC Resampling for Higher Resolution Conversion
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Solution Overview
Problem
Conventional analog-to-digital converters (ADCs) face significant increases in circuit area and power consumption as resolution increases, requiring more capacitors and control units, which limits the improvement of resolution due to the need for doubled area and power consumption with each doubling of resolution.
Innovation Solution
The ADC resamples and reconverts the remaining part of the input signal after initial conversion, using a basic N-bit configuration with 1st to N−1 voltage selection units and capacitors, allowing for higher than N-bit resolution without a proportional increase in area or power consumption by employing a capacitor array with specific capacitance ratios and voltage selection strategies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the resolution of the ADC is increased, then the measurement precision is improved, but the area of the ADC increases significantly
Solution Approach 1:
The patent divides the ADC conversion process into multiple stages: a first ADC performs initial conversion of the input signal, and a second ADC converts the remaining signal. This segmentation allows the system to achieve high overall resolution without requiring a single large high-resolution ADC, thereby reducing the total circuit area while maintaining measurement precision.
2Measurement precision
If the resolution of the ADC is increased, then the measurement precision is improved, but the power consumption increases significantly
Solution Approach 1:
The patent segments the conversion process into two stages using two separate ADCs. Each ADC operates at lower resolution individually, but together they achieve high overall resolution. This segmentation reduces power consumption because lower-resolution ADCs consume less power than a single high-resolution ADC would require.
3Measurement precision
If the number of capacitors is increased to improve resolution, then the measurement precision is improved, but the area of the ADC increases more than proportionally
Solution Approach 1:
The patent divides the capacitor array into two separate sets: one set for the first ADC and another set for the second ADC. Each ADC uses its own capacitors to perform conversion on different portions of the signal. This segmentation allows the system to achieve high resolution without requiring one large capacitor array, thereby reducing the total capacitor area while maintaining measurement precision.
4Measurement precision
If the number of control units is increased to improve resolution, then the measurement precision is improved, but the device complexity increases
Solution Approach 1:
The patent divides the control functionality into two separate control units, each managing one ADC. Each control unit generates control signals for its respective ADC's voltage selection units and switching units. This segmentation simplifies the control logic compared to a single high-resolution ADC, as each control unit only needs to manage a smaller portion of the conversion process, thereby reducing device complexity while maintaining measurement precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables higher resolution digital signal conversion with reduced ADC area and power consumption, achieving 2N−1 bit resolution using a basic N-bit ADC configuration, with iterative resampling and conversion operations.
Implementation Method 1
1st to Nth capacitors having one ends connected to the input node, respectively... In a sampling step, the input signal is applied to the other ends of the capacitors C1 to CN, so that the capacitors C1 to CN are charged
Data Source
AI summary
An analog-to-digital converter includes a comparison unit that outputs a result obtained by comparing a voltage of an input node with a comparison voltage; 1st to Nth capacitors having one ends connected to the input node, respectively; and 1st to N−1th voltage selection units corresponds to the 2nd to Nth capacitors, respectively and applies one of a voltages of a 1st node, a 2nd node, and the comparison voltage to the other ends of the corresponding capacitors. An input signal is sampled to the input node, the 1st to N−1th voltage selection units select one of the voltages of the 2 nodes and convert a part of the input signal into a 1st digital signal, and the 1st to N−1th voltage selection units select one of the voltages of the 2 nodes and convert the remaining part of the input signal into a 2nd digital signal.