Integrate-and-Fire ADC Residual Charge Sensing for Small Currents
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Solution Overview
Problem
Existing slope ADCs using the integrate-and-fire principle face limitations in achieving high resolution (above 14 bits) and wide dynamic range while maintaining a compact size and low power consumption, particularly when measuring small currents (0.1 to 250 nA) with high accuracy and speed.
Innovation Solution
The method involves converting an input analog signal into a digital value by applying it to an integrator, removing charge from an integration capacitor at a reference voltage, counting events, measuring residual time, and determining the digital value based on event counts and residual time, without using complex circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the integration capacitor is reduced to decrease residual charge, then measurement precision improves, but the dynamic range decreases
Solution Approach 1:
The patent segments the measurement process into two distinct phases: a first integration phase that captures the full dynamic range of input signals, and a second integration phase that measures only the residual charge with high precision. This segmentation allows the system to achieve both wide dynamic range and high resolution without compromising either parameter.
Solution Approach 2:
The patent applies preliminary action by performing a first integration phase before the second integration phase. The first integration phase pre-processes the signal by integrating it over a longer period, establishing a baseline that enables the subsequent high-precision measurement of residual charge in the second phase, thereby achieving both dynamic range and resolution.
2Measurement precision
If the integration time is increased to improve resolution, then measurement precision improves, but the conversion speed decreases
Solution Approach 1:
The patent employs periodic action by dividing the conversion process into two distinct integration phases with different time durations. The first phase uses a longer integration time for capturing the full signal range, while the second phase uses a shorter integration time for measuring residual charge. This periodic structure enables high resolution without sacrificing overall conversion speed.
Solution Approach 2:
The first integration phase serves as a preliminary action that prepares the system for the second phase. By performing the initial integration beforehand, the system establishes conditions that allow the second phase to achieve high resolution quickly, thereby maintaining fast conversion speed while improving measurement precision.
3Measurement precision
If a complex circuit structure is used to measure residual charge, then measurement precision improves, but device complexity increases
Solution Approach 1:
The patent applies self-service by using the existing integrator circuit to measure its own residual charge. The same integrator that performs the initial integration is reused in the second phase to measure the residual charge, eliminating the need for separate measurement circuits. This self-service approach achieves high precision while keeping the device simple.
Solution Approach 2:
The integrator circuit is designed with multi-functionality, serving both as the primary integration element for signal conversion and as the measurement instrument for residual charge detection. This universal use of the integrator across different phases eliminates the need for additional dedicated measurement circuits, thereby reducing device complexity while maintaining high measurement precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances resolution beyond 14 bits by measuring residual charge in the integration capacitor, reducing quantization errors, and maintaining a simple circuit structure with low power consumption.
Implementation Method 1
an integrator with an integrator capacitor and an integration clock controlling the overall conversion process
Implementation Method 2
an integrator voltage decreases until it reaches a threshold voltage defined by a comparator which then triggers an event
Data Source
Figure 1~2
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Figure 6~7
AI summary
The present disclosure relates to a method for converting an input analog signal into an output digital value, the method comprising: applying the input analog signal (Ic) to an integrator (OP1) for an integration period (Ti); removing a charge quantity in an integration capacitor (CI) of the integrator, each time an output voltage (Vi) of the integrator reaches a reference voltage (Vcr); generating an event in an event signal (EVT) each time the integrator voltage reaches the reference voltage; generating an event count value (DO) by counting the events during an integration period; at the end of the integration period, continuing to generate events; determining a residual time (Tr) from a last event to the end of the integration period; and determining an output digital value corresponding to the input analog signal as a function of the event count value (DO) and the residual time.