Sequential ADC Sampling Clock Control by Reference Voltage Detection
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Solution Overview
Problem
Sequential comparison type AD conversion circuits face issues with extra sampling time due to the characteristics of the AD conversion circuit or operating conditions, leading to inefficient use of external clock duty ratio.
Innovation Solution
An AD conversion circuit with a reference voltage generator and a sampling time controller that detects the rising reference voltage threshold to determine sampling completion, generating a sampling clock to control sampling time based on an external clock, allowing for flexible adjustment of sampling time without fixed designs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If fixed sampling time is used based on external clock duty ratio, then AD conversion circuit operation is simplified, but extra sampling time occurs reducing efficiency
Solution Approach 1:
The sampling time controller dynamically adjusts the sampling time period based on the actual stabilization state of the reference voltage, transitioning from a fixed time approach to a dynamic adaptation approach. This allows the system to optimize sampling time in real-time, eliminating extra sampling time while maintaining operational simplicity.
Solution Approach 2:
The sampling time controller monitors the reference voltage stabilization state and uses this feedback information to determine when sampling should be performed. This feedback mechanism enables the system to automatically adjust sampling timing, reducing wasted time while keeping the control logic simple.
2Reliability
If longer sampling time is allocated to ensure AD conversion completion, then conversion reliability is improved, but external clock frequency is limited
Solution Approach 1:
The system dynamically determines sampling time based on actual reference voltage stabilization rather than using a fixed conservative time allocation. This dynamic approach ensures sufficient time for reliable conversion while allowing the external clock to operate at higher frequencies, thus improving overall system speed.
Solution Approach 2:
The sampling time parameter is changed from a fixed value to a variable that adapts based on reference voltage stabilization characteristics. This parameter change allows the system to maintain reliable conversion completion while accommodating higher external clock frequencies, effectively resolving the trade-off between reliability and speed.
3Ease of manufacture
If fixed duty ratio design is used for external clock, then circuit design is simplified, but adaptability to different specifications is reduced
Solution Approach 1:
The sampling time controller dynamically adapts the sampling time period based on reference voltage stabilization, replacing the need for fixed duty ratio designs. This dynamic approach maintains circuit design simplicity while significantly improving adaptability to different user specifications and operating conditions.
Solution Approach 2:
The sampling time controller serves multiple functions: it monitors reference voltage stabilization, determines optimal sampling timing, and adjusts sampling time dynamically. This multi-functionality allows a single circuit design to adapt to various specifications without requiring fixed duty ratio configurations, enhancing versatility while maintaining design simplicity.
Data Source
AI summary
A reference voltage generator generates a reference voltage at the time of sampling a received input signal. A sampling time controller detects a change in the reference voltage. When the reference voltage rises to a determined threshold, the sampling time controller determines that sampling is completed, and generates a sampling clock in which sampling time is controlled on the basis of an external clock.