ADC Sampling Correction Using Clock Deviation Indication
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Solution Overview
Problem
Electronic data processing systems face errors due to clock jitter when analog-to-digital and digital-to-analog converters sample data at frequencies other than the ideal system clock frequency, leading to timing inaccuracies.
Innovation Solution
A system comprising a clock generator module and a correction module that derive a digital clock from the system clock, generating a deviation indication to correct sampling errors caused by jitter, using a non-integer derivation of clock cycles and interpolation factors to adjust sample values.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a digital clock is derived from the system clock using non-integer division to achieve a different frequency, then the clock frequency flexibility is improved, but timing inaccuracies and jitter increase
Solution Approach 1:
The patent pre-calculates and stores correction factors in a lookup table before the actual sampling process. The correction factors, which compensate for jitter, are determined in advance based on the known clock derivation ratios, allowing the system to apply corrections without real-time computation delays
Solution Approach 2:
The patent introduces a correction module as an intermediary between the ADC and the digital signal processing chain. This module uses the pre-calculated correction factors to adjust the sampled values, effectively mediating the timing inaccuracies introduced by non-integer clock division
2Measurement precision
If the system uses integer division of the system clock to generate a digital clock, then timing accuracy is maintained, but the ability to sample at non-integer frequencies is lost
Solution Approach 1:
The patent changes the parameters of the clock signal by allowing non-integer division ratios. By accepting that the clock frequency will deviate from ideal integer divisions, the system gains the ability to sample at frequencies that are not simple fractions of the system clock
Solution Approach 2:
The patent converts the harmful effect of jitter into a beneficial correction mechanism. By characterizing the jitter pattern through pre-calculated correction factors, the system transforms what would be pure noise into a correctable distortion, actually improving overall system performance
3Productivity
If correction factors are pre-calculated and stored in a lookup table, then correction speed is improved, but memory requirements increase
Solution Approach 1:
The patent implements a partial lookup table strategy where only the most frequently used correction factors are pre-calculated and stored. Less common correction factors are calculated on-demand, balancing the trade-off between correction speed and memory usage
Data Source
AI summary
A system comprising includes a clock generator module, an analog-to-digital converter (ADC), and a correction module. The clock generator module receives a system clock and generates a digital clock that is derived from the system clock, wherein the digital clock has an average frequency. The clock generator module generates a deviation indication that indicates a deviation of the digital clock from an ideal clock of the average frequency. The ADC receives an analog signal, receives the digital clock, and generates a first stream of values by sampling the analog signal at intervals based on the digital clock. The correction module receives the first stream of values and generates a second stream of values that are corrected based on the deviation indication.