ADC Selection Circuit With Adjustable Resolution and Low Delay
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Solution Overview
Problem
Conventional analog-to-digital converting circuits face limitations in conversion speed, power consumption, and chip area, with flash ADCs being power-intensive and expensive, pipelined ADCs causing latency, and successive approximation ADCs having increased conversion time with the number of bits.
Innovation Solution
The proposed circuit includes a first and second comparison circuit, a selection circuit, and a resolution adjustment mechanism to perform analog-to-digital conversion without delay, allowing for intermediate digital signal generation and resolution adjustment based on user input, enabling efficient conversion and accumulation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If flash ADC is used for fast conversion, then conversion speed is improved, but power consumption and chip area increase significantly
Solution Approach 1:
The patent divides the conversion process into two stages: a first conversion stage producing a first digital signal, and a second conversion stage producing a second digital signal. This segmentation allows the system to achieve fast conversion without requiring all comparators to operate simultaneously, thereby reducing power consumption while maintaining conversion speed.
Solution Approach 2:
The patent implements dynamic resolution adjustment where the resolution of the second conversion stage is adjusted based on the first digital signal result. This dynamic adaptation allows the system to optimize power consumption by reducing the number of comparators needed in the second stage when lower precision is sufficient, while maintaining high conversion speed when full precision is required.
2Speed
If flash ADC is used for fast conversion, then conversion speed is improved, but chip area increases due to multiple comparators
Solution Approach 1:
The conversion process is segmented into multiple stages with different resolution requirements. The first conversion stage handles the most significant bits, and the second stage handles the least significant bits. This segmentation reduces the total number of comparators needed compared to a single-stage flash ADC, thereby reducing chip area while maintaining fast conversion speed.
Solution Approach 2:
The patent applies partial action by implementing a second conversion stage with adjustable resolution that processes only when needed. The resolution of the second stage is dynamically adjusted based on the first digital signal, allowing the system to use fewer comparators in the second stage when full precision is not required, thus reducing chip area while maintaining conversion speed.
3Speed
If pipelined ADC is used for fast conversion, then conversion speed is improved, but delay or latency occurs in the conversion
Solution Approach 1:
The patent performs preliminary conversion in the first conversion stage to generate a first digital signal that provides initial conversion results. This preliminary action allows the second conversion stage to start processing simultaneously rather than sequentially, reducing the overall conversion delay while maintaining fast conversion speed.
Solution Approach 2:
The patent changes the temporal dimension of conversion by implementing parallel processing in two conversion stages. Instead of sequential processing that causes pipeline delay, the system processes different bit groups simultaneously in parallel stages, eliminating the cumulative delay inherent in pipelined architectures while maintaining fast conversion.
4Use of energy by stationary object
If successive approximation ADC is used to reduce chip area and power consumption, then chip area and power are reduced, but conversion period increases by time corresponding to the number of bits
Solution Approach 1:
The patent segments the conversion process into two stages: a first conversion stage that quickly produces a first digital signal, and a second conversion stage that refines the result. This segmentation allows the system to achieve accurate conversion without requiring the sequential bit-by-bit processing of successive approximation ADC, thereby reducing the conversion period while maintaining low power consumption.
Solution Approach 2:
The first conversion stage performs preliminary conversion to generate an initial digital result that provides a head start for the final conversion. This preliminary action eliminates the need for sequential bit testing from most significant to least significant bit, reducing the conversion period while maintaining the low power consumption characteristics of successive approximation methods.
Data Source
AI summary
An analog-to-digital converting circuit includes a first comparison circuit configured to compare a first analog signal associated with a first digital signal with an analog input signal and output a first selection signal based on a result of the comparison, a second comparison circuit configured to compare a second analog signal associated with a second digital signal with the analog input signal and output a second selection signal based on a result of the comparison, and a selection circuit configured to generate intermediate digital signals associated with the first digital signal and output one of the intermediate digital signals as the first digital signal and another of the intermediate digital signals as the second digital signal, based on the first selection signal and the second selection signal.