ADC Selective Count Storage for Power Reduction
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Solution Overview
Problem
Current analog-to-digital conversion technologies, such as single slope ADCs in column-parallel architectures, face limitations in readout speed and increased power consumption, while pixel-parallel architectures consume large amounts of power due to numerous pixel ADCs, especially in high-resolution applications.
Innovation Solution
The proposed analog-to-digital converter employs a comparison circuit and processing circuit to selectively store a count value from a counter circuit based on the comparison of an analog signal with a ramp signal and a ramp signal plus a predetermined offset, reducing power consumption by enabling storage only when the analog signal level falls within a specific range, and using a global counter shared among multiple ADCs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If pixel-parallel architecture with numerous pixel ADCs is used, then conversion capability is improved, but power consumption increases significantly
Solution Approach 1:
Multiple ADC channels share a single counter circuit, merging the counter resource to serve multiple conversion channels simultaneously, reducing the total number of active circuits and thereby lowering power consumption while maintaining conversion capability
Solution Approach 2:
The counter circuit is enabled selectively during specific periods when conversion is needed rather than continuously operating, using periodic enable signals to activate the counter only when required, thus reducing average power consumption
2Reliability
If continuous storage of count value is enabled, then data availability is improved, but power consumption increases
Solution Approach 1:
The storage circuit is controlled to store count values only during specific periods when the analog signal level falls within the predetermined range, rather than continuously storing, thereby reducing power consumption while ensuring data is available when needed
Solution Approach 2:
The system preliminarily determines whether the analog signal level is within the predetermined range before enabling storage, using comparison circuits to assess conditions in advance and only activate storage when appropriate, avoiding unnecessary power consumption
3Speed
If multiple parallel ADC channels are used, then readout speed is improved, but device complexity increases
Solution Approach 1:
Multiple ADC channels share common resources including a single counter circuit and storage circuit, merging these components to serve multiple channels, thereby reducing overall circuit complexity while maintaining parallel processing capability for high readout speed
Solution Approach 2:
The shared counter circuit and storage circuit are designed to be universal, capable of serving multiple ADC channels through multiplexing and control signals, allowing one circuit to perform multiple functions across different channels, reducing total component count
Data Source
AI summary
An analog-to-digital converter is provided. The analog-to-digital converter is configured to convert an analog signal to a digital signal. The analog-to-digital converter includes a comparison circuit and a processing circuit. The comparison circuit is configured to compare the analog signal with each of a ramp signal and the ramp signal plus a predetermined offset to generate a control signal. The processing circuit, coupled to the comparison circuit, is configured to selectively store a count value of a counter circuit as the digital signal according to the control signal. When the control signal indicates that a signal level of the analog signal is greater than a signal level of the ramp signal and less than the signal level of the ramp signal plus the predetermined offset, the processing circuit is configured to store the count value as the digital signal.