On-Chip ADC Self-Test Using RF DAC Signal Generation
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Solution Overview
Problem
The high cost and complexity of conventional RF analog test setups in manufacturing make ADC testing time-consuming and expensive, necessitating a more efficient method for on-chip self-testing.
Innovation Solution
A semiconductor chip with integrated on-chip self-testing capabilities, including a DAC to generate RF test signals, a reference data generation circuit, and a comparator circuit to determine quantization errors, allowing for Built-In Self Test (BIST) functionality without external equipment, using a 1-bit DAC with a mixed-signal FIR filter output stage for high spectral purity and harmonic suppression.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional RF analog test setup is used for ADC testing, then measurement precision is achieved, but test time and device complexity increase significantly
Solution Approach 1:
The patent implements built-in self-test functionality where the ADC device tests itself using integrated test signal generation circuits and error calculation logic, eliminating the need for external specialized test equipment and significantly reducing test time while maintaining measurement precision
Solution Approach 2:
The patent combines the test signal generation, ADC conversion, error calculation, and test control functions into a single integrated chip, merging previously separate test equipment components into one unified self-testing system that reduces both test time and device complexity
2Measurement precision
If conventional RF analog test setup is used for ADC testing, then measurement precision is achieved, but device complexity and cost increase
Solution Approach 1:
The ADC device performs self-testing using built-in test signal generation and error calculation circuits, eliminating the need for complex external RF analog test equipment and reducing overall device complexity while maintaining measurement precision
Solution Approach 2:
The patent creates a simplified digital model of the test signal and expected output, comparing it with actual ADC output to determine errors, replacing complex analog test equipment with a digital copying and comparison approach
3Loss of time
If on-chip self-testing is implemented, then test time is reduced, but device complexity increases
Solution Approach 1:
The patent divides the self-testing functionality into distinct modular components: test signal generation circuit, ADC converter, error calculation circuit with subtractor and absolute value circuit, and control logic, allowing each segment to be optimized independently while reducing overall complexity
Solution Approach 2:
The patent uses parameter changes in the error calculation process, transforming the error signal through absolute value calculation and digital processing to generate pass/fail indicators, simplifying the complexity of direct analog error measurement
Data Source
AI summary
A semiconductor chip providing on-chip self-testing of an Analog-to-Digital Converter, ADC, implemented in the semiconductor chip is provided. The semiconductor chip comprises the ADC and a Digital-to-Analog Converter, DAC, configured to generate and supply a radio frequency test signal to the ADC via a supply path. The ADC is configured to generate digital output data based on the radio frequency test signal. The semiconductor chip further comprises a reference data generation circuit configured to generate digital reference data. Additionally, the semiconductor chip comprises a comparator circuit configured to compare the digital output data to the digital reference in order to determine error data.