ADC Sequencer and FIFO Control for Fewer Converter Channels
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The demand for analog to digital converters (ADCs) has increased in modern electronic applications, particularly in motor control devices, but the available number of ADCs is often insufficient, and existing systems require microprocessor intervention for management and conversion sequence control.
Innovation Solution
An analog to digital conversion apparatus featuring an input multiplexor circuit, an analog to digital conversion circuitry, a conversion starting device, a sequencer, and a FIFO register block that allows for efficient management and execution of multiple conversion sequences without microprocessor intervention, using a multiplexor circuit, sequencer, and FIFO register block to handle multiple analog input signals and trigger events.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple ADCs are used to handle multiple conversion sequences, then the conversion capability and reliability are improved, but the device complexity and cost increase
Solution Approach 1:
The patent implements a single ADC that can handle multiple conversion sequences by introducing a sequencer and FIFO register block. The sequencer controls the ADC to execute different conversion sequences based on instructions from the FIFO, allowing one ADC to perform the work of multiple ADCs. This multi-functional approach resolves the contradiction by maintaining conversion capability while reducing the number of ADC components needed.
Solution Approach 2:
The patent introduces intermediate control components (sequencer and FIFO register block) between the microcontroller and the ADC. The FIFO stores conversion sequence instructions, and the sequencer automatically manages the conversion process based on these instructions. This intermediary mechanism allows the single ADC to be efficiently managed for multiple conversion sequences without requiring multiple ADCs or continuous microprocessor intervention.
2Adaptability or versatility
If a microprocessor is used to manage ADC conversion sequences, then the conversion management flexibility is improved, but the processing time and system complexity increase
Solution Approach 1:
The patent implements the FIFO register block to store conversion sequence instructions in advance. Before the actual conversion process begins, the conversion sequences are pre-configured and queued in the FIFO. The sequencer then automatically executes these pre-prepared sequences without requiring real-time microprocessor intervention. This preliminary action resolves the contradiction by providing management flexibility through pre-configured sequences while eliminating time loss from continuous processor involvement.
Solution Approach 2:
The patent enables the ADC system to manage its own conversion sequences autonomously through the sequencer and FIFO mechanism. Once the FIFO is loaded with instructions, the sequencer automatically controls the ADC execution without needing the microprocessor. This self-service capability resolves the contradiction by maintaining flexibility in conversion management while eliminating the time penalty and complexity of continuous microprocessor control.
3Productivity
If the ADC processes multiple conversion sequences continuously, then the productivity is improved, but the risk of instruction loss or error increases
Solution Approach 1:
The patent introduces the FIFO register block as a buffer between the microcontroller and the sequencer. The FIFO can queue multiple conversion sequence instructions, providing a cushion that decouples the instruction loading rate from the execution rate. This buffer prevents instruction loss during high-speed processing by storing instructions in advance, resolving the contradiction by enabling continuous high-productivity operation while maintaining reliability through the protective buffer.
Solution Approach 2:
The patent implements a status flag mechanism that provides feedback about the ADC conversion state. The sequencer monitors conversion completion and uses this feedback to determine when to load the next instructions from the FIFO. This feedback loop ensures that instructions are executed in the correct sequence and prevents errors by synchronizing instruction loading with conversion completion, thereby maintaining reliability during continuous high-productivity operation.
Data Source
AI summary
An analog to digital conversion includes a multiplexor circuit for receiving analog input signals and, responsive to a select input, an analog to digital converter circuit to convert a selected analog signal into a digital signal, a conversion starting device to send a conversion start signal on the basis of a trigger event, the conversion starting device being responsive to a select input, a sequencer to control the analog to digital converter circuitry to execute one sequence conversion on the basis of one conversion sequence instruction, and a FIFO register block to receive conversion sequence instructions and being able to queue each new received conversion sequence instruction if an actual conversion sequence is in progress and to control the sequencer to execute a new sequence conversion instruction after the conversion sequence is executed.