Programmable ADC Sequencer Architecture for Multi-Input Sampling
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing Analog to Digital Converter (ADC) units in microcontrollers lack programmability and flexibility, relying on single or double-sampling approaches that require frequent reconfiguration and microcontroller core intervention, limiting their ability to handle multiple input sources efficiently.
Innovation Solution
A programmable ADC unit with multiple programmable sample sequencers and FIFO registers, allowing user-defined sequences and event-initiated sampling, enabling efficient data collection from multiple inputs without reconfiguration, and prioritizing events for concurrent processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If existing ADC units use single or double-sampling approaches, then the device complexity is reduced, but the adaptability and productivity deteriorate due to frequent reconfiguration and microcontroller core intervention
Solution Approach 1:
The ADC unit is segmented into multiple independent sample sequencers (first, second, third, and fourth programmable sample sequencers), each capable of autonomous operation with its own FIFO register. This segmentation allows each sequencer to handle different sampling sequences independently, improving adaptability without requiring the entire ADC unit to be reconfigured, thus resolving the contradiction between programmability and device complexity.
Solution Approach 2:
The ADC unit implements dynamic programmability where sample sequencers can be configured with variable sequence lengths (e.g., maximal lengths of {8, 4, 4, 1} for different sequences) and prioritization levels. This dynamic configuration capability allows the system to adapt to different sampling requirements without fixed hardware constraints, enhancing versatility while maintaining manageable complexity through structured design.
2Productivity
If existing ADC units require frequent reconfiguration and microcontroller core intervention, then the device complexity is reduced, but the productivity deteriorates due to inability to handle multiple input sources efficiently
Solution Approach 1:
Each sample sequencer is equipped with its own FIFO (First-In-First-Out) register block, enabling autonomous data buffering without requiring microcontroller core intervention. The sequencers can independently collect and buffer data from multiple analog inputs according to their programmed sequences, significantly improving productivity by eliminating the bottleneck of frequent CPU intervention while the modular structure keeps complexity manageable.
Solution Approach 2:
The ADC unit enables continuous data collection from multiple input sources through multiple concurrent sample sequencers operating in parallel. Each sequencer can continuously sample its assigned inputs and fill its FIFO buffer without interruption or reconfiguration, ensuring continuous useful action across all input channels simultaneously, thereby improving overall productivity without requiring complex time-division multiplexing.
3Reliability
If existing ADC units use non-prioritized event processing, then the device complexity is reduced, but the reliability deteriorates due to inability to handle concurrent events effectively
Solution Approach 1:
The event control mechanism implements local quality through differentiated prioritization where different sample sequencers can be assigned different priority levels (e.g., first sequencer with highest priority, fourth with lowest). This allows critical sampling sequences to be processed reliably even under heavy load, while less critical sequences can yield. The localized priority assignment to individual sequencers maintains reliability without requiring a monolithic complex control structure.
Solution Approach 2:
The control/status register block serves as an intermediary that manages the prioritization and coordination between multiple sample sequencers and trigger events. It receives trigger events, determines priority based on configured levels, and routes events to appropriate sequencers without requiring direct complex interactions between all components. This intermediary structure improves reliability of event processing while keeping the overall control mechanism manageable through centralized arbitration.
Data Source
AI summary
The present invention is a programmable Analog to Digital Converter (ADC) unit (200) that includes an analog to digital converter (204), which includes one or more analog inputs (202). The unit (200) additionally includes a control/status register block (216). The unit 200 further includes a FIFO register block (206) with a first, second, third, and fourth FIFO conversion register. Further included is a programmable sequencer (300) that includes a first (208), second (210), third (212), and fourth (214) programmable sample sequencer. And further, the unit (200) includes a first (226), second (228), third (230), and fourth (232) trigger event control multiplexer, where each trigger event control multiplexer corresponds to each programmable sample sequencer.