ADC Sampling Front-End With Shared Residue Amplification
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Solution Overview
Problem
Time-interleaved analog to digital converters (ADCs) used in battery-powered mobile applications face challenges with sampling mismatches and conversion speed due to capacitive DAC structures, which affect power consumption and performance.
Innovation Solution
A sampling front-end architecture that shares an N-bit ADC among multiple time-interleaved residue amplification units, where the ADC samples an analog input signal and generates residues, which are then amplified and shared among units, eliminating sampling mismatches by performing time-interleaving only during residue amplification, and utilizing a compact capacitive digital-to-analog converter structure with low parasitic and high density layout to enhance conversion speed and reduce power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If time-interleaved scheme is used for high speed ADC, then conversion speed is improved, but sampling mismatches occur between different channels
Solution Approach 1:
The ADC system is segmented into multiple residue amplification units (i units) that operate in parallel, each handling a portion of the conversion process. The N-bit ADC is shared among these units, allowing high-speed operation while maintaining accuracy through the segmented architecture that processes residues independently.
Solution Approach 2:
The N-bit ADC performs preliminary conversion of the input signal before the residue amplification stages. By completing the initial N-bit conversion first and then processing residues through the amplification units, the system achieves high speed while the preliminary action ensures accurate sampling before time-interleaved processing begins.
2Use of energy by moving object
If capacitive DAC structure is used in ADC, then power consumption is reduced, but conversion speed is affected
Solution Approach 1:
The capacitive DAC structure parameters are optimized to achieve low power consumption while maintaining high conversion speed. The patent employs carefully designed capacitance values and switching configurations that minimize power dissipation during charge transfer operations while ensuring fast settling times for accurate residue amplification.
Solution Approach 2:
The patent replaces traditional voltage-based DAC mechanisms with capacitive charge transfer mechanisms. This substitution allows for lower power consumption since capacitive switching requires minimal current, while the fast charge transfer characteristics of capacitors maintain high conversion speed through efficient charge redistribution among the capacitive elements.
3Productivity
If multiple ADC channels are implemented, then conversion speed is improved, but device complexity increases
Solution Approach 1:
The N-bit ADC is designed as a universal resource that serves multiple residue amplification units. This single ADC performs the initial conversion for all i channels, eliminating the need for separate ADCs for each channel. The time-interleaved residue amplification units share the common ADC, reducing overall system complexity while maintaining high conversion throughput through parallel processing of residues.
Data Source
AI summary
A sampling front-end for analog to digital converter is presented that shares a high speed N-bit ADC at front-end and interleaves the pipelined residue amplification with shared amplifier, which achieves high speed, low power and compact area with high density capacitive DAC structure.