ADC Shift-Register Conversion for Fewer Clock Cycles
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Solution Overview
Problem
Conventional analog-to-digital converters require a significant number of clock signals to determine digital codes, leading to slow conversion of analog signals into digital codes.
Innovation Solution
An analog-to-digital converter design that includes a code voltage generating part, a voltage comparing part, a shifting register, and a code generating part, which generates conversion digital codes quickly by sequentially activating control pulse signals without overlap, allowing for efficient determination of digital bits based on comparison results.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional successive approximation ADC uses sequential clock generation for digital-to-analog conversion, then the conversion process is systematic and reliable, but the conversion time becomes excessively long requiring up to 15 clock cycles for 4-bit conversion
Solution Approach 1:
The patent applies preliminary action by pre-generating all necessary control pulse signals (first through fourth control pulse signals) in advance using a shifting register before the actual conversion process begins. This allows the conversion to proceed through multiple stages simultaneously rather than sequentially, reducing the number of clock cycles from 15 to 4 for 4-bit conversion while maintaining systematic control and reliability
Solution Approach 2:
The patent segments the conversion process into four distinct stages, each controlled by a separate control pulse signal. Each stage handles a specific bit position (first bit, second bit, third bit, fourth bit), allowing parallel processing of conversion operations. The shifting register generates these segmented control signals that activate different portions of the digital-to-analog converter simultaneously, achieving faster conversion without sacrificing reliability
2Measurement precision
If the ADC converts digital code from highest value to lowest value sequentially, then each bit determination is accurate and reliable, but the total number of clock signals required increases to 15 for 4-bit conversion
Solution Approach 1:
The patent implements continuity of useful action by maintaining active conversion operations across all four stages simultaneously through continuous clock signal generation. The shifting register continuously produces control pulse signals that keep the digital-to-analog converter and comparator operating without idle clock cycles. This continuous operation reduces total conversion time from 15 clock cycles to 4 clock cycles while preserving measurement precision through systematic bit-by-bit determination in each stage
Data Source
AI summary
An analog-to-digital converter may comprise a code voltage generating part that generates a conversion code voltage according to the conversion digital code; a voltage comparing part that generates a comparison result signal by comparing the input analog voltage and the conversion code voltage; a shifting register that receives a clock signal and generates a 1-st to a n-th control pulse signals; and a code generating part that generates the conversion digital code with receiving by comparison result signal and the 1-st to the n-th control pulse signals.