Sigma-Delta ADC Shuffler Stability for DAC Mismatch Noise Shaping
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Solution Overview
Problem
Conventional sigma-delta analog-to-digital converters (ΣΔ ADCs) face instability issues with second-order shufflers when input signals are not zero-mean, leading to unbounded accumulation and degradation of signal-to-noise ratio (SNR) due to mismatch errors in DAC unit elements.
Innovation Solution
A stability-corrected second-order shuffler is introduced, incorporating accumulation correctors to suppress saturation and maintain second-order frequency shaping, thereby minimizing noise and improving SNR by compensating for mismatch errors between DAC unit elements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If second-order shuffler is used to minimize mismatch noise in frequency of interest, then noise minimization is improved, but stability deteriorates when input signals are not zero-mean
Solution Approach 1:
The patent implements a stability correction mechanism that monitors the accumulation values in the second-order shuffler and applies corrective feedback to prevent saturation. The correction logic detects when accumulation values approach saturation thresholds and adjusts the shaping filter coefficients dynamically to maintain stability while preserving the second-order noise shaping performance.
Solution Approach 2:
The patent introduces dynamic adaptation to the static second-order shuffler structure by making the shaping filter coefficients variable rather than fixed. The system dynamically adjusts these coefficients based on the input signal characteristics and accumulation state, allowing the shuffler to maintain stability for non-zero-mean inputs while preserving second-order noise shaping for zero-mean inputs.
2Stability of the object's composition
If accumulation correctors are added to prevent saturation, then stability is improved, but device complexity increases
Solution Approach 1:
The stability correction mechanism is designed to be self-regulating, automatically detecting saturation conditions and applying corrections without external intervention. The system monitors its own accumulation values and adjusts its coefficients autonomously, eliminating the need for external stability control circuits or manual calibration.
Solution Approach 2:
Instead of adding substantial hardware complexity, the patent achieves stability correction by dynamically changing the parameters (coefficients) of the existing shuffler structure. This approach maintains the core second-order noise shaping architecture while introducing only minimal additional logic for parameter adjustment, thereby achieving stability improvement with limited complexity increase.
3Object-affected harmful factors
If saturation is suppressed to maintain second-order frequency shaping, then noise minimization is preserved, but operational constraints increase
Solution Approach 1:
The patent makes the shuffler adaptive to different input signal types by dynamically adjusting its coefficients based on the input characteristics. For zero-mean inputs, the system operates in pure second-order mode for optimal noise shaping. For non-zero-mean inputs, it automatically transitions to a stabilized mode that prevents saturation while maintaining effective noise reduction, thereby accommodating diverse input signals without manual configuration.
Data Source
AI summary
A sigma-delta analog-to-digital converter (“ΣΔ ADC”) may include a loop filter, ADC, a feedback digital-to-analog converter (“DAC”), and a control circuit. The feedback DAC may include several unit elements (resistors, capacitors, or current sources) that, ideally, are identical to each other but vary due to mismatch errors introduced during manufacture. Mismatch errors may introduce signal errors that generate undesirable noise frequencies and non-linearities in a ΣΔ ADC output signal. Embodiments of the present invention provide a stability corrected second order shuffler that allows for the shaping of the frequency response by the ΣΔ ADC to reduce the effect of the mismatch error between DAC unit elements. The second order shuffler may include accumulation correctors, to suppress saturation for accumulators within the shuffler. The suppression may compress the range of accumulation values for each accumulator while maintaining context for the values to stabilize operation of the second order shuffler.