Time-Interleaved ADC Skew Calibration Using Multi-Tone Injection

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Solution Overview

Problem

Time-interleaved ADCs suffer from timing skew errors that degrade performance, particularly at high frequencies, due to dynamic sampling time mismatches between channels, which are challenging to correct.

Innovation Solution

A time-interleaved ADC circuit with an input signal amplitude detector, multi-tone signal generator, and digital output subtractor module, which generates and applies fixed frequency signals dependent on input amplitude to correct timing errors by synchronizing and subtracting reference tones from the output, using an iterative least mean square algorithm for skew calibration.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If time-interleaved ADC channels are used to achieve high sampling rates, then sampling frequency is improved, but timing skew errors between channels increase

Engineering Contradiction:
Improvesampling frequencyVSAvoidtiming skew error
Core Design Contradiction:
SpeedVSMeasurement precision

Solution Approach 1:

The patent applies preliminary action by performing skew calibration before actual signal conversion. A calibration phase is executed first to measure and correct timing skews between ADC channels using test signals, establishing corrected timing relationships before the ADC operates on real input signals. This preliminary calibration step prevents timing skew errors from degrading the high sampling rate performance.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements feedback through an iterative skew calibration process. The system measures timing skew errors between ADC channels using test signals, calculates correction values, applies these corrections, and repeats the measurement to verify improvement. This closed-loop feedback continues until timing skew errors are reduced below a threshold, ensuring high precision is maintained at high sampling rates.

Inventive Principle:
Principle #23Feedback

2Measurement precision

If skew calibration is performed to reduce timing errors, then measurement precision is improved, but device complexity increases

Engineering Contradiction:
Improvetiming skew accuracyVSAvoidcalibration circuit complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent applies self-service by designing an automated skew calibration system that performs its own calibration without external intervention. The ADC circuit includes built-in calibration logic that automatically generates test signals, measures timing skews, calculates correction values, and applies corrections to the ADC channels. This self-calibrating approach reduces the need for complex external calibration equipment and manual adjustment circuits.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The patent uses parameter changes by dynamically adjusting the timing parameters of ADC channels based on measured skew errors. The calibration process modifies sampling phase parameters and timing offset parameters of individual ADC channels to compensate for manufacturing variations and environmental effects. These parameter adjustments are applied through digital control signals that modify the operation of ADC channels without changing their physical structure.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS12425039B2Time-interleaved ADC skew correction
Publication Date: 2025.09.23 NXP BV
  • US12425039B2 patent drawing
  • US12425039B2 patent drawing
  • US12425039B2 patent drawing

AI summary

A time-interleaved analog to digital converter (ADC) circuit includes an input signal amplitude detector configured to determine an input signal amplitude of an analog input signal, a multi-tone signal generator configured to generate a plurality of analog and digital sinusoidal signals having an amplitude dependent on the determined input signal amplitude, and an analog input summing module configured to provide a summed output analog signal from the analog input signal and the analog sinusoidal signals. A time-interleaved ADC has an input coupled to receive the summed output analog signal from the analog input summing module and configured to provide a timing skew-calibrated digital output signal from the summed output analog signal. A digital output subtractor module is configured to provide a digital output signal at an output of the circuit from the digital output signal from the time-interleaved ADC and the digital sinusoidal signals from the multi-tone signal generator.