ADC Slice Calibration for Offset Error Without Speed Loss
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Solution Overview
Problem
Analog-to-digital converters (ADCs) face performance degradation due to transistor mismatches, leading to offset voltage errors, which are typically addressed by increasing transistor size, resulting in speed degradation or increased power consumption.
Innovation Solution
The implementation of a calibration method for ADCs that includes a digital to analog converter (DAC), a comparator, and a digital processing unit, which samples comparator outputs, adjusts the input signal based on calibration conditions, and uses a signal conditioning element like an amplifier to reduce mismatch offset voltage without increasing transistor size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If transistor size is increased to reduce mismatch offset voltage, then manufacturing precision is improved, but speed is degraded
Solution Approach 1:
The patent applies preliminary action by performing calibration before normal ADC operation. A calibration mode is activated that uses a calibration signal generator to generate test signals, allowing the system to measure and correct offset voltages in advance. This preliminary calibration step establishes correction values that are stored and applied during normal operation, eliminating the need for large transistors while maintaining precision.
Solution Approach 2:
The patent changes operational parameters by switching between calibration mode and normal conversion mode. During calibration, the system generates specific test signals and measures offset voltages to determine correction values. These parameter changes allow the system to optimize performance without requiring physically larger transistors, thus maintaining speed while improving precision.
2Manufacturing precision
If transistor size is increased to reduce mismatch offset voltage, then manufacturing precision is improved, but power consumption is increased
Solution Approach 1:
The calibration process is performed preliminarily to establish correction values once, rather than continuously during normal operation. This preliminary action allows the system to achieve precision without requiring large transistors that would consume excessive power during normal conversion operations.
Solution Approach 2:
The system employs periodic action by activating calibration mode at specific intervals or under specific conditions rather than continuously. The calibration signal generator and correction mechanisms are engaged periodically to update correction values, while normal conversion operations proceed with stored corrections, thereby reducing overall power consumption compared to continuously operating large transistors.
3Speed
If bandwidth is increased to compensate for speed degradation, then speed is improved, but power consumption is increased
Solution Approach 1:
The system applies self-service by automatically generating calibration signals and performing self-diagnosis of offset voltages without requiring external calibration equipment. The calibration signal generator and digital processing unit work together to autonomously measure and correct errors, eliminating the need for additional power-consuming external calibration apparatus while maintaining high bandwidth and speed performance.
Data Source
AI summary
Methods, systems, and apparatuses for calibration of analog to digital converters (ADC) are described herein. In an aspect, an ADC includes a plurality of slices. Each slice includes a digital to analog converter (DAC), a comparator, and a digital processing unit (DPU). The digital processing unit is electrically connected to the comparator and the DAC. In another aspect, an analog-to-digital converter includes an input module and an analog to digital converter core configured to receive an analog input from the input module and generate a digital output. The ADC is configured to adjust a precision of the analog to digital converter core based on a quality of the analog input signal.