Clock Data Recovery Using ADC Slope Analysis for Low-Latency Timing
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Solution Overview
Problem
Existing communication systems face reliability issues due to timing skew of clocks caused by environmental factors, leading to latency and jitter in signal communication, particularly when using multi-level signals.
Innovation Solution
A receiving device evaluates clock timing using outputs from an analog-to-digital converter without relying on equalizer outputs, employing a delay buffer, phase interpolator, and clock data restorer to determine slope and curve types, thereby adjusting clock phase compensation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If Mueller-Muller Phase Detection (MMPD) is used to detect clock phase with low power, then power consumption is reduced, but loop latency increases due to the impact of clock timing search on the loop connected to ADC
Solution Approach 1:
The patent extracts the clock phase detection function from the equalizer output path and directly uses ADC output samples for phase evaluation. This separates the phase detection process from the equalization process, allowing low-power operation without the latency penalty of waiting for equalizer convergence.
Solution Approach 2:
The patent performs clock phase evaluation using ADC outputs before equalizer processing is complete. By using preliminary ADC samples directly for phase detection, the system avoids the delay that would otherwise be incurred waiting for equalizer output, thus reducing loop latency while maintaining low power consumption.
2Measurement precision
If equalizer output is used for clock phase detection, then phase detection accuracy may be improved, but loop latency occurs due to the impact of clock timing search on the loop connected to ADC
Solution Approach 1:
The patent extracts phase detection capability from the equalizer output dependency and implements it using ADC outputs directly. This extraction allows the system to achieve sufficient phase detection accuracy without waiting for the equalizer to process the signal, thereby eliminating the associated loop latency.
3Reliability
If timing skew of clock is adjusted using traditional methods, then communication reliability is improved, but device complexity increases due to the loop structure connecting ADC, Equalizer, CDR, and Phase Interpolator
Solution Approach 1:
The patent extracts the clock phase detection function from the complex loop structure and implements it using a simplified path that directly uses ADC outputs. This extraction maintains communication reliability by accurately detecting clock phase while significantly reducing the complexity of the loop structure by eliminating the dependency on equalizer output and simplifying the feedback path.
Data Source
AI summary
A receiving device includes a delay buffer configured to receive an analog signal and output a delayed analog signal, a phase interpolator configured to output a clock signal based on a phase compensation code signal and a reference clock signal, an analog-to-digital converter group configured to output a slope type determination signal indicating a slope of the analog signal based on the analog signal and the delayed analog signal, and a clock data restorer. The clock data restorer is configured to determine a curve type associated with a plurality of digital samples from the analog-to-digital converter group. The clock data restorer also evaluates a timing of the clock signal based on the curve type and the slope type determination signal, and outputs the phase compensation code signal to move the sample timing closer to an optimum timing.