ADC Speed Calibration Using Extra Bit-Trials Under PVT Variation
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Solution Overview
Problem
The variation in Process (P), Voltage (V), and Temperature (T) (PVT) poses a challenge in calibrating the speed of analog-to-digital converter (ADC) circuits, particularly in ultra-low power applications, where the circuit speed can vary significantly, affecting power consumption and accuracy.
Innovation Solution
The ADC circuit performs M bit-trials during the conversion phase and additional X bit-trials during a calibration mode to estimate conversion and acquisition times, allowing for the adjustment of comparison time, DAC settling delay, and logic propagation delay to calibrate its operational mode conversion time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If separate calibration circuitry is added to calibrate ADC conversion time, then measurement precision improves, but device complexity increases
Solution Approach 1:
The ADC circuit is designed to perform both normal conversion operations and calibration measurements using the same circuitry. The calibration mode reuses the comparator, DAC, and logic circuits already present in the ADC, eliminating the need for separate calibration equipment and reducing overall device complexity while maintaining calibration accuracy.
Solution Approach 2:
The ADC circuit performs self-calibration by using its own internal resources. The calibration process leverages the ADC's built-in comparator and logic circuits to measure conversion time and automatically adjust calibration parameters, making the system self-sufficient and eliminating external calibration equipment.
2Productivity
If calibration is performed in parallel with operational mode, then productivity improves, but device complexity increases
Solution Approach 1:
The ADC operates in periodic cycles, alternating between normal conversion mode and calibration mode. During each calibration cycle, the ADC temporarily switches to calibration operations, performs conversion time measurements, adjusts calibration parameters, then returns to normal operation. This time-division approach enables calibration without requiring parallel operational modes.
Solution Approach 2:
The calibration process is performed periodically in advance to establish accurate conversion time parameters before normal high-speed conversion operations begin. By pre-calibrating the circuit using the bit-trial method, the system ensures accurate timing parameters are available for subsequent operational modes without requiring simultaneous calibration.
Data Source
AI summary
A conversion time and an acquisition time of an ADC can be estimated so that a speed of the ADC can be calibrated. An ADC circuit can perform M bit-trials in its conversion phase and continue performing additional bit-trials in a calibration mode. The ADC can count the number of additional bit-trials performed, e.g., X bit-trials, that occur before the next conversion phase, where additional bit-trials can be considered to be the number of available bit-trials during an acquisition time if the ADC continues performing bit-trials instead of sampling an input signal. The ADC can estimate the conversion time and the acquisition time using M and X. Then, the conversion time of the ADC can be calibrated by adjusting one or more of the comparison time, DAC settling delay, and logic propagation delay.