ADC Speed-Up Comparison Mechanism for Fast Accurate Conversion
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Solution Overview
Problem
Conventional digital slope analog-to-digital conversion circuits are too time-consuming due to their slower operation speed.
Innovation Solution
An analog-to-digital conversion circuit with a speed-up comparison mechanism, utilizing a positive capacitor array, a negative capacitor array, comparators, and a control circuit that switches capacitors at different speeds based on the difference between positive and negative output voltages, operating in speed-up or normal modes depending on the voltage difference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional digital slope analog-to-digital conversion circuit uses linear capacitor switching to track input signal, then conversion accuracy is maintained, but operation speed becomes slow and conversion time increases
Solution Approach 1:
The patent applies dynamics by making the capacitor switching speed variable rather than fixed. The control circuit dynamically adjusts the switching speed between first capacitor switching speed and second capacitor switching speed based on the voltage difference magnitude detected by comparators. This allows the system to adapt its operation mode (speed-up or normal) to match the instantaneous signal conditions, resolving the contradiction between speed and accuracy
Solution Approach 2:
The patent changes the parameter of capacitor switching speed from a constant value to a variable parameter. By switching between two different capacitor switching speeds (first and second speeds) based on the voltage difference, the system can optimize performance for different operating conditions. This parameter change enables fast conversion when voltage difference is large while maintaining accuracy when voltage difference is small
2Productivity
If capacitor switching speed is increased to improve operation speed, then conversion time is reduced, but accuracy may be compromised when voltage difference is small
Solution Approach 1:
The patent uses parameter changes by implementing two distinct capacitor switching speeds. The control circuit selects the appropriate switching speed parameter based on the voltage difference magnitude. When voltage difference exceeds the reference voltage, the faster first capacitor switching speed is used to improve productivity. When voltage difference is within the reference range, the slower second capacitor switching speed is used to maintain accuracy, thus resolving the contradiction between productivity and precision
3Device complexity
If single capacitor switching speed is used, then circuit complexity is reduced, but operation speed cannot be optimized for different voltage difference conditions
Solution Approach 1:
The patent applies dynamics by implementing a dynamic capacitor switching mechanism controlled by comparators and a control circuit. The system dynamically selects between two capacitor switching speeds based on real-time voltage difference detection. This dynamic approach optimizes operation speed for different conditions while maintaining reasonable circuit complexity through structured control logic
Solution Approach 2:
The patent segments the capacitor switching operation into two distinct modes: speed-up mode and normal mode. Each mode uses a different capacitor switching speed appropriate for specific voltage difference conditions. This segmentation allows the system to optimize performance for different operating scenarios without requiring a completely complex circuit design
Data Source
AI summary
The present invention discloses an analog-to-digital conversion circuit having speed-up comparison mechanism. Each of a positive and a negative capacitor arrays receives a positive and a negative input voltages to generate a positive and a negative output voltages. A first comparator performs comparison thereon to generate a first comparison result and a second comparator performs comparison according to a reference voltage to generate a second comparison result. A control circuit switches a capacitor enabling combination of the capacitor arrays according to the first comparison result and outputs a digital code as a digital output signal when the positive and the negative output voltages equal. The control circuit operates in a speed-up switching mode when a difference between the positive and the negative output voltages is outside of a predetermined range defined by the reference voltage and operates in a normal switching mode when the difference is within the predetermined range.