ADC Start-Up Timing With Fixed-Latency Conversion Triggers
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Solution Overview
Problem
Current microcontrollers face challenges in maintaining a fixed and predictable latency between the triggering and actual start time of analog-to-digital conversions, especially when the clock frequencies of the timer and converter have high frequency ratios, leading to performance alterations.
Innovation Solution
An integrated circuit design that includes a processor controlling an analog-to-digital converter with a timer, using a first operating mode to clock the timer synchronously with the converter clock signal, delivering a periodic conversion control signal with a fixed phase difference, and a second mode to clock asynchronously, allowing selection between these modes based on application needs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the timer and converter are clocked by synchronous clocks, then a fixed latency is obtained, but the converter clock frequency must be limited to a maximum of 75 MHz while the timer can operate at several hundred MHz
Solution Approach 1:
The patent segments the clocking system into two independent parts: the timer operates at high frequency (several hundred MHz) while the converter operates at its optimal frequency (up to 75 MHz). The timer generates multiple conversion triggers per PWM period, and the converter selectively processes only those triggers that occur during its active sampling window, thereby achieving both high timer speed and precise latency control.
Solution Approach 2:
The patent introduces dynamic control mechanisms including a converter status signal that indicates when the converter is ready to accept triggers, and a trigger selection logic that dynamically selects which timer triggers to pass to the converter. This dynamic coordination allows the system to maintain fixed latency while operating at different optimal frequencies for each component.
2Productivity
If the timer operates at high frequency (several hundred MHz) and the converter at lower frequency (up to 75 MHz), then the timer can provide more triggers per period, but the latency between triggering and conversion start becomes variable
Solution Approach 1:
The patent implements a preliminary synchronization mechanism where the timer is configured to generate triggers at specific predetermined phases relative to the converter clock. The system pre-calculates and pre-positions triggers so that even though the timer runs at higher frequency, only triggers occurring at the correct phase are passed to the converter, ensuring consistent latency while maintaining high productivity.
Solution Approach 2:
The patent introduces an intermediary control mechanism consisting of the converter status signal and trigger selection logic. This intermediary layer sits between the high-frequency timer and the lower-frequency converter, filtering and synchronizing triggers to ensure that latency remains fixed while allowing the timer to operate at high speed for increased conversion rate.
3Manufacturing precision
If pseudo-synchronous clocks with low frequency ratios (2 or 4) are used, then a fixed latency is obtained, but the converter performances are altered
Solution Approach 1:
The patent changes the frequency ratio parameter from low values (2 or 4) to high values (several hundred MHz / 75 MHz), while compensating for the potential performance degradation through intelligent trigger selection and synchronization mechanisms. The system maintains fixed latency by controlling which triggers are passed to the converter, not by forcing a low frequency ratio.
Data Source
AI summary
An analog-to-digital converter is clocked by a converter clock signal. A first clock signal has a frequency multiple of the frequency of the converter clock signal. A timer, which is clocked with the rhythm of the first clock signal, has a timing period multiple of the period of the converter clock signal. A processor is configured to control the converter based on the timing signal delivered by the timer, and has a first operating mode in which it is further configured to clock the timer synchronously with the converter clock signal and to deliver based on the timing signal, a periodic first conversion control signal of the converter, having a period multiple of the period of the converter clock signal and a constant first phase difference with the converter clock signal.