Successive Approximation ADC Step Selection With Multi-Cycle Feedback
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Solution Overview
Problem
Conventional successive approximation analog to digital converters (SA-ADCs) are slow and consume high power due to the need for accurate comparisons and long recursion cycles, which are not efficiently reduced by existing methods like overlapping half-range selection.
Innovation Solution
A circuit that generates reference signals for a comparator under control of successive digital reference values, using output signals from multiple preceding recursion cycles to select steps, allowing for faster convergence and reduced power consumption by narrowing the range of uncertain values without extending recursion cycle duration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional middle-value comparison method is used in SA-ADC, then the comparison accuracy is maintained, but the conversion speed is slow due to long settling time requirements
Solution Approach 1:
The patent uses comparator output signals from preceding recursion cycles to predict and determine the direction of the next step in the digital reference value series. This preliminary use of historical comparison data allows the system to anticipate the convergence direction, reducing the settling time required for each subsequent comparison while maintaining accuracy.
Solution Approach 2:
The patent implements feedback by using the comparator output signals from previous recursion cycles to influence the selection of digital reference values in current and future cycles. This feedback mechanism allows the system to learn from past comparisons and optimize the convergence path, achieving faster conversion speed without sacrificing measurement precision.
2Measurement precision
If overlapping half-range selection method is used, then the comparison accuracy requirement is reduced, but the conversion speed improvement is limited and power consumption remains high
Solution Approach 1:
The patent employs feedback from multiple preceding recursion cycles to determine step directions, allowing the system to achieve accurate convergence without requiring high-precision comparisons at each step. This reduces the comparison accuracy requirement while maintaining fast conversion speed and lowering power consumption by avoiding the need for multiple parallel comparators.
Solution Approach 2:
The patent changes the parameter of step size in the digital reference value series by selecting steps based on historical comparator outputs. Instead of fixed step sizes or simple overlapping ranges, the system dynamically adjusts step directions using feedback, achieving efficient convergence with reduced power consumption and improved productivity.
3Speed
If parallel comparison with two thresholds is performed to improve speed, then the conversion speed increases, but the circuit area increases due to requiring two comparators
Solution Approach 1:
The patent uses preliminary comparison results from preceding recursion cycles to determine the direction of subsequent steps. This preliminary action eliminates the need for parallel comparisons, achieving fast conversion speed while maintaining a compact circuit design with a single comparator.
Solution Approach 2:
The patent implements a feedback mechanism that uses historical comparator outputs to guide future comparison directions. This single-comparator feedback approach achieves the same speed improvement as parallel comparisons would provide, but without the increased circuit area requirement.
4Speed
If parallel comparison is used to improve speed, then the conversion speed increases, but the power consumption increases due to increased number of comparisons
Solution Approach 1:
The patent uses feedback from preceding recursion cycles to determine step directions, reducing the total number of comparisons needed for convergence. This approach achieves fast conversion speed while minimizing power consumption by avoiding the redundant comparisons that would be performed by parallel comparator architectures.
Data Source
AI summary
During successive approximation analog to digital conversion a series of successive digital reference values is selected that converges towards a digital representation of an analog input signal. An analog reference signal is generated dependent on the successive digital reference values and compared to the analog input signal. The digital reference values are selected dependent on comparison results. In the selection of the digital reference values successive steps between digital reference values are each selected dependent on values of the comparator result from a plurality of preceding recursion cycles. The comparison results define a series of successively narrower ranges of digital values that contain a digital representation of the analog input signal. Use of a plurality of comparator results for selecting the steps in the digital reference values makes it possible to reduce uncertainty about whether the comparison result has settled. This in turn makes it possible to reduce the sizes of the successive ranges, which speeds up convergence.