ADC Switched Capacitor Voltage Regulators
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Solution Overview
Problem
Existing communication devices face challenges in efficiently converting analog signals to digital due to constant supply voltages, leading to increased power consumption and performance degradation, as prior methods like linear and switching regulators fail to provide optimal voltage levels for varying sampling frequencies and bandwidths.
Innovation Solution
The implementation of switched capacitor voltage regulators within Analog to Digital Converters (ADCs) that generate adjustable voltages and grounds using complementary and non-overlapping clocks, allowing for extended sampling ranges and minimizing noise, thereby optimizing power supply for ADC operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If linear regulators are used to generate ADC voltages, then wider sampling ranges can be achieved, but power consumption increases
Solution Approach 1:
The patent uses switched capacitor voltage regulators to dynamically adjust voltage levels based on ADC operating conditions. The regulators change voltage parameters in response to varying sampling frequencies and signal ranges, achieving adaptability without the continuous power dissipation of linear regulators. This resolves the contradiction by providing wide sampling ranges only when needed, rather than maintaining fixed voltage levels.
2Use of energy by moving object
If switching regulators are used to generate ADC voltages, then power consumption is reduced, but I/O pin count and part count increase
Solution Approach 1:
The patent integrates the switched capacitor voltage regulators directly into the ADC chip, merging previously separate regulator components with the ADC core. This integration eliminates external I/O pins and reduces part count while maintaining the power efficiency benefits of switching regulation. The regulators share substrate and routing resources with the ADC, resolving the complexity issue.
3Adaptability or versatility
If external regulators are used to provide ADC voltages, then voltage flexibility is improved, but performance degrades due to power supply spurs
Solution Approach 1:
The patent introduces switched capacitor voltage regulators as intermediary elements between the power supply and ADC core. These regulators act as mediators that filter and condition power delivery, reducing power supply spurs while maintaining voltage flexibility. The regulators are specifically designed with noise reduction techniques to eliminate harmful spurs that degrade ADC performance.
4Device complexity
If constant supply voltages are used, then device simplicity is maintained, but ADC performance degrades for varying sampling frequencies
Solution Approach 1:
The patent implements dynamic voltage regulation within the ADC using switched capacitor circuits that adjust voltage levels in real-time based on sampling frequency and signal characteristics. This dynamic adaptation maintains signal conversion accuracy across varying operating conditions without requiring complex external voltage control systems. The internal regulators respond automatically to changing ADC requirements.
Data Source
AI summary
An Analog to Digital Converter (ADC) includes an ADC core, a first switched capacitor voltage regulator, and a second switched capacitor voltage regulator. The ADC core includes a plurality of digital components that sample an incoming signal based on an ADC clock, a first voltage, and a first ground and a plurality of analog components configured to operate using a second voltage and a second ground. The first switched capacitor voltage regulator produces the first voltage and the first ground for the plurality of digital components using a supply voltage, a supply ground, and the ADC clock. The second switched capacitor voltage regulator produces the second voltage and the second ground using the supply voltage, the supply ground, and the ADC clock. Switching of the first and second switched capacitor voltage regulators is performed using complementary and non-overlapping clocks having switching frequency that is based upon the ADC clock.