Switched-Capacitor ADC Switching Timing for Charge Loss Reduction
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Solution Overview
Problem
Switched capacitor analog to digital converters (ADCs) experience charge losses due to negative transient voltage at summing terminals, leading to gain error, gain error drift, and non-linearity performance degradations, especially when operating at low supply voltages and high signal-to-noise ratios.
Innovation Solution
The circuit employs NMOS and PMOS transistors configured in parallel to control the electrical connection and disconnection of sampling and DAC terminals during sampling and transfer phases, with specific timing of gate signals to minimize negative transient voltage, including a slower falling edge for the first PMOS transistor and concurrent rising edge for NMOS transistors to ensure balanced charge redistribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If a low ADC core supply voltage is used to achieve power efficiency, then power consumption is reduced, but charge losses occur due to negative transient voltage at summing terminals
Solution Approach 1:
The patent applies preliminary action by controlling the switching sequence of transistors to prevent negative transient voltage before it can cause charge losses. Specifically, the first PMOS transistor is turned on before the second and third PMOS transistors during the transfer phase, which prepares the summing terminal voltage in advance to avoid the harmful negative transient that would otherwise lead to charge losses from the sampling capacitors and DAC capacitors.
2Speed
If NMOS and PMOS transistors are switched simultaneously during transfer phase to improve speed, then transfer speed increases, but negative transient voltage causes charge losses
Solution Approach 1:
The patent applies segmentation by dividing the transistor switching operation into distinct phases with different timing. Instead of switching all transistors simultaneously, the first PMOS transistor is switched on before the second and third PMOS transistors, and the NMOS transistors are switched on after the PMOS transistors. This segmented approach maintains high transfer speed while preventing the negative transient voltage that causes charge losses.
Solution Approach 2:
The patent applies dynamics by making the switching timing of different transistors dynamic and sequential rather than static and simultaneous. The gate signals for the first PMOS transistor, second/third PMOS transistors, and NMOS transistors are timed differently to create an optimized switching sequence that adapts to the charge transfer process, thereby maintaining speed while eliminating charge losses.
3Productivity
If fast switching of all transistors is used to improve productivity, then charge transfer speed increases, but negative transient voltage results in gain error and non-linearity
Solution Approach 1:
The patent applies preliminary action by preparing the summing terminal voltage in advance through controlled switching of the first PMOS transistor before the other transistors. This preliminary preparation prevents the negative transient voltage that would otherwise cause gain error and non-linearity, thereby maintaining high charge transfer efficiency while ensuring measurement precision.
Solution Approach 2:
The patent applies dynamics by implementing a dynamic switching sequence where different transistors are switched at different times. The first PMOS transistor switches on before the second and third PMOS transistors, and NMOS transistors switch on after the PMOS transistors. This dynamic timing maintains high productivity while preventing gain error and non-linearity by avoiding negative transient voltage.
Data Source
AI summary
Circuits and methods for minimizing charge losses due to negative transient voltage at summing terminals of an analog to digital converter (ADC) are disclosed. The ADC is coupled to a multi-bit digital to analog converter (DAC) at the summing terminals. The ADC and the DAC include PMOS and NMOS transistors whose timing are controlled to reduce charge losses. The PMOS transistors are turned ON before the NMOS transistors. Also, the PMOS transistor of the ADC is turned ON at a slower rate than the PMOS transistors of the DAC.