ADC Temporal Separation for Priority-Based Multi-Point Sampling
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Solution Overview
Problem
Existing analog-to-digital converters (ADCs) in microcontrollers face challenges in efficiently handling multiple measurements of specific points on a signal waveform due to interruptions during data buffer juggling and Interrupt Service Routines, requiring sequential reading and management, which can be inefficient and costly in terms of resources and timing.
Innovation Solution
An ADC circuit with temporal separation features, including channel register sets, a conversion request flip-flop, priority encoder circuit, and controller circuit, allows for flexible channel assignment and priority-based conversion selection, enabling simultaneous processing of distinct values from multiple points on a waveform without software intervention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If sequential reading and buffer management is used in conventional ADCs, then software can process measurements, but software overhead and latency increase during control loop cycles
Solution Approach 1:
The patent segments the data buffer into multiple dedicated registers (DATA0-DATA7) that can be independently accessed. Each register is associated with specific analog inputs through channel register sets, allowing parallel access to multiple measurement points without sequential buffer management. This segmentation eliminates the need for software to juggle a single buffer, thereby reducing software overhead and latency.
Solution Approach 2:
The patent implements preliminary action by pre-configuring channel register sets that define the relationship between analog inputs and data registers before measurements are taken. The channel registers store the mapping information in advance, so when measurements are acquired, the data can be directly placed into the correct registers without requiring software intervention to determine storage location. This pre-configuration reduces processing latency during control loop cycles.
2Adaptability or versatility
If multiple measurements are taken at different points on a waveform, then comprehensive signal analysis is achieved, but sequential access and buffer management complexity increase
Solution Approach 1:
The patent divides the data storage structure into multiple dedicated registers (DATA0-DATA7), each capable of holding measurements from specific analog input combinations. This segmentation allows the system to simultaneously capture multiple waveform points (such as peak and valley) in separate registers without requiring complex buffer management software to track and organize the data. The channel register sets further segment the configuration space to map analog inputs to specific data registers.
Solution Approach 2:
The channel register sets automatically configure the mapping between analog inputs and data registers, enabling the system to self-manage multiple measurement points without external software intervention. When measurements are taken at different waveform points, the hardware automatically routes each measurement to the appropriate dedicated register based on the pre-configured channel settings, eliminating the need for complex software buffer management while maintaining comprehensive signal analysis capability.
3Productivity
If dedicated registers are used for each data channel, then parallel access and processing are enabled, but hardware resources increase
Solution Approach 1:
The patent implements universality by designing channel register sets that can be configured to support multiple measurement scenarios using the same hardware structure. The channel registers can define various combinations of analog inputs mapping to data registers, allowing the same hardware to adapt to different application requirements (such as measuring peak and valley, or multiple analog inputs) without requiring additional dedicated hardware for each scenario. This multi-functionality enables parallel data processing while controlling hardware resource growth.
Data Source
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AI summary
Embodiments of the present disclosure may include an ADC circuit including channel register sets, a conversion request flip-flop, a priority encoder circuit, and a controller circuit. The controller circuit may be configured to receive a conversion request signal, latch the conversion request signal into the conversion request flip-flop, determine by the priority encoder circuit a highest priority pending conversion request, and output an active channel identifier code. The channel identifier code may be configured to select the data channel register sets that are active by identifying received selection bits. The embodiments may include logic to store a converted value from a selected analog input to a data output register based on the channel identifier code.