On-Chip ADC Testing Using Shared Memory and DAC Resolution Scaling
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge lies in efficiently testing analog-mixed signal circuits on-chip, particularly analog-to-digital converters (ADCs), using limited on-chip memory, where existing methods struggle to accommodate the storage needs for calibration and test data within the constrained memory space.
Innovation Solution
The implementation of a memory engine that interleaves and manages calibration data and test data within the 32KB on-chip RAM, allowing for mutually exclusive operation by varying the resolution of the digital-to-analog converter (DAC) during testing of different types of ADCs, such as SDADCs and SARADCs, ensuring effective use of memory space without the need for data compression.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If on-chip testing of ADCs is performed using available on-chip memory, then the number of external devices is reduced and testing speed is improved, but the limited memory size cannot accommodate both calibration data and test data
Solution Approach 1:
The on-chip memory is segmented into multiple banks (first bank and second bank) that can be independently accessed. Calibration data is stored in one bank while test data is stored in another bank, allowing simultaneous operations without data conflicts and maximizing memory utilization for both purposes
Solution Approach 2:
The patent introduces a bank selection dimension to the memory architecture. By adding the bank select signal, the system can access different memory banks independently, effectively doubling the available memory capacity for simultaneous calibration and test operations without increasing the physical memory size
2Measurement precision
If calibration data for high-resolution DAC is stored in on-chip memory, then accurate testing of SDADCs is enabled, but memory space is completely occupied leaving no room for test data
Solution Approach 1:
The memory is divided into separate banks where one bank is dedicated to storing high-resolution calibration data while another bank is allocated for test data. This segmentation allows the system to maintain full calibration accuracy for SDADC testing while simultaneously having space available for test operations
Solution Approach 2:
The multi-bank memory structure provides universal access capabilities where different banks can serve different functions simultaneously. The system can perform calibration operations using one bank while conducting test operations using another bank, making the memory system versatile for multiple purposes
3Quantity of substance
If external devices are used for ADC testing, then sufficient storage space is available, but testing time increases and on-chip testing capability is lost
Solution Approach 1:
The patent merges the calibration data storage and test data storage functions into a single on-chip memory structure with multiple banks. This integration eliminates the need for external memory devices while providing sufficient storage capacity for both calibration and test operations, thereby reducing testing time and maintaining on-chip testing capability
Data Source
Figure 1
Figure 2
Figure 3
AI summary
Analog-to-digital converters (ADCs) of an integrated circuit includes a first set of ADCs and second set of ADCs in which the ADCs of the first set are of a different type than the ADCs of the second set. On-chip testing of the ADCs includes calibrating an N-bit differential digital-to-analog converter (DAC) and storing a pair of calibration codes for each of 2N possible DAC input codes for the DAC in an on-chip memory. The first set of ADCs is tested using the pairs of calibration codes stored in the on-chip memory and a full N-bit resolution of the DAC. Subsequently, the second set of ADCs is tested using pairs of calibration codes corresponding to a reduced M-bit resolution of the DAC, in which M is less than N. During the testing of the second set of ADCs, a portion of the calibration codes stored in the on-chip memory is overwritten.