ADC Timestamp Tagging for Inter-Chip Timing Uncertainty

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Solution Overview

Problem

In systems where a measurement apparatus and a controller are formed in separate semiconductor chips, the lack of a common clock source leads to uncertainty in timing relationships between analog signals and digital data, causing issues in data interpretation and transmission.

Innovation Solution

The integration of an Analog-to-Digital Converter (ADC) in the measurement apparatus transforms analog signals into a modulated digital data stream combined with event indication data, which is then transmitted in a communication frame to the controller, allowing the controller to determine the timing relationship without needing to know the specific acquisition time of the analog signal.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If the measurement apparatus and controller are formed in separate semiconductor chips, then device integration flexibility is improved, but timing relationship precision deteriorates due to lack of common clock source

Engineering Contradiction:
Improvedevice integration flexibilityVSAvoidtiming relationship precision
Core Design Contradiction:
Adaptability or versatilityVSMeasurement precision

Solution Approach 1:

The patent introduces an intermediary mechanism (timestamp counter and communication frame structure) that mediates between the measurement apparatus and controller. The timestamp counter captures timing information from the measurement apparatus's local clock, and this timestamp is transmitted through the communication interface to the controller, allowing the controller to determine acquisition times without needing a common clock source. This intermediary approach enables separate chips to maintain precise timing relationships.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Measurement precision

If a common clock source is used between measurement apparatus and controller, then timing relationship precision is improved, but device complexity increases due to synchronization requirements

Engineering Contradiction:
Improvetiming relationship precisionVSAvoidsynchronization complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent extracts the timing information from the complex synchronization problem by separating the timestamp generation from the data acquisition process. The timestamp counter independently captures timing information, which is then packaged with the digital data in a communication frame. This extraction approach simplifies the system by eliminating the need for complex inter-chip synchronization while maintaining precise timing relationships.

Inventive Principle:
Principle #2Taking out (Extraction)

3Productivity

If digital data is transmitted without event indication data, then communication efficiency is improved, but data interpretation reliability deteriorates due to timing uncertainty

Engineering Contradiction:
Improvecommunication efficiencyVSAvoiddata interpretation reliability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent merges the digital data stream with event indication data (timestamps) into a unified communication frame structure. The timestamp counter generates event indication data that is combined with the converted digital data before transmission. This merging ensures that each data packet contains both the measurement value and its corresponding timing information, enabling reliable data interpretation without requiring separate synchronization channels or reducing communication efficiency.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS10848354B2Combined data and timing information
Publication Date: 2020.11.24 INFINEON TECHNOLOGIES AG
  • US10848354B2 patent drawing
  • US10848354B2 patent drawing
  • US10848354B2 patent drawing

AI summary

A measurement apparatus for providing digital data to a controller, including an Analog-to-Digital Converter (ADC) configured to transform an analog signal into a modulated digital data stream; an event detector configured to generate event indication data based on an event related to the analog signal or the digital data; and a communication interface configured to combine the modulated digital data stream and the event indication data into one or more communication frames, and to transmit the one or more communication frames to the controller.